Lattice Semiconductor introduced an evaluation board for the ispClock 5400D programmable clock device. The evaluation board is an easy-to-use platform for evaluating and designing with the ispClock5400D differential clock distribution device. The evaluation board can be used by itself to review the performance and in-system programmability of the 5400D device, or as a companion board and clock source for LatticeECP3 FPGA Serial Protocol or Video Protocol evaluation boards. The ispClock5400D evaluation board is priced at $169.
Lattice Semiconductor ispClock5400D Evaluation Board Contents
- ispClock5406D Evaluation Board
- ispDOWNLOAD Cable (HW-USBN-2A)
- Universal AC Adapter
- QuickSTART Guide
The ispClock5400D evaluation board is a versatile, ready to use hardware development platform for evaluating and designing with ispClock programmable clock devices. The platform is based on a 6″ x 4″ evaluation board that features the ispClock 5406D device in a lead-free 48-pin QFNS package, SMA connectors and crystal oscillator circuits, as well as expansion headers for JTAG, I2C bus and test. The kit includes a preconfigured ispClock5400D demonstration design that illustrates the low-jitter performance and time/phase skew output control of the device. The board is controlled with switches and push buttons. A pin header provides access to the I2C bus interface of the ispClock5406D device.
Expensive oscillators with LVDS or LVPECL interfaces are used as a reference clock for FPGA SERDES interface applications. The ispClock5400D device provides ultra low-jitter differential clock outputs that can be used to drive both the general purpose clocks and the SERDES reference clocks for FPGAs, ASSPs and ASICs. The evaluation board demonstrates how to interface a low-cost CMOS interface oscillator to the ispClock5400D device to produce high quality clocks for XAUI applications or 270 MHz SDI video applications.
More info: Lattice ispClock 5400D Evaluation Board