Evatronix SA introduced their C80186XL and C6502 soft IP cores. The cores are aimed at original chip replacement applications. Significant effort was undertaken to achieve the degree of reliability that guarantees trouble-free porting of the existing software to FPGA or ASIC based core implementations. C6502 and C80186XL IP cores are available for licensing immediately. Netlist or full source code, single or multiple use licences are available. Other versions of the 80186 architecture might be developed under Evatronix’ design services contract according to customer needs.
The C6502 IP core features extreme efficiency – it takes as little as 2.4K gates at 79MHz when area optimized and 3.2K gates at 177MHz when speed optimized for ASIC technology. FPGA speed optimized implementations of the C6502 require no more than 390 slices in Xilinx FPGAs, while area optimized ones require slightly more than 300 slices.
The C80186XL is a high performance 16-bit microprocessor IP core designed to be a pin replacement of Intel[tm] 80c186xl chip. The core implements the same widely known instruction set as its chip predecessor, as well as an identical set of peripherals – Timer and Refresh Control Units, two independent DMA channels. The architecture, which derives from the speed-optimized C80186TX design, allows fast development of other 80186-compliant IP cores that would replace the following chips: 80c186ea, 80c186ec by Intel[tm] or AM186ER, AM186ED, AM186ES by AMD[tm].
Both designs are strictly synchronous with a synchronous reset and no internal tri-states. The provided set of functional inputs, outputs and control signals make creation of a pin compatible device a straightforward task. The cores are also an appealing solution for low volume applications; the C80186XL can be easily implemented into the inexpensive Altera device (Cyclone III EP3C16).
More info: Evatronix