Achronix Bridge100 Platform 120 Gbps Reprogrammable Networking System

The Achronix Bridge100 Platform is a 120 Gbps Infiniband-to-Ethernet programmable platform designed to put high-performance capability into the hands of communications systems designers. The fully reprogrammable Bridge100 features an array of 1.5 GHz Achronix SPD60 FPGAs, 8 GB of additional on-board memory (upgradeable to 32GB), and two 120 Gbps communication ports that give designers access to the full performance, memory, bandwidth, capacity, and flexibility required in today’s high-performance networking applications.

Achronix Bridge100 Platform 120 Gbps Reprogrammable Networking System

Achronix Bridge100 Platform Highlights

  • Bridge100 board is built on Speedster 1.5 GHz FPGAs and its patented picoPIPE acceleration technology and 10.3 Gbps SerDes
  • The Achronix Bridge100 board is a flexible dual interface system supporting 120 Gbps bandwidth
  • Optimized for 100 Gbps Infiniband-to-Ethernet applications, the Bridge100 board offers 3 QSFPs for 120 Gbps of Infiniband connectivity, 12 XFPs for 120 Gbps Ethernet connectivity, and 546 Gbps DDR3 bandwidth

The Achronix Bridge100 platform offers two 120 Gbps bidirectional interfaces: three QSFP connectors on one side, and 12 XFP connectors on the other. All Speedster high-performance FPGA features are available, including logic, RAMs, multipliers, SerDes, programmable I/Os and the Achronix patented picoPIPE acceleration technology. The programmable logic takes the form of an array of SPD60s from the Achronix Speedster family of FPGAs.

The high datapath bandwidth of each SPD60 (10.3 Gbps SerDes) provides more than enough bandwidth to support two 100 Gbps interfaces (Ethernet, Infiniband). Additional SerDes lanes are used in 60 Gbps chip-to-chip links, effectively fusing the SPD60s into one “megachip.” Each SPD60 provides up to 273 Gbps of raw DDR3 memory bandwidth.

The Bridge100 includes eight DDR3 modules, a QDRII+ memory, and a NetLogic Search Engine (CAM). The memory is in addition to the 3.3 Mb per SPD60 (30 Mb total) embedded in the FPGA devices. The ample memory resources are available for packet buffering, classification, scheduling and traffic shaping, and statistics gathering. The features of the Speedster family (logic performance, SerDes and DDR3 bandwidth), are the foundation for the Bridge100.

More information: Achronix Bridge100 (pdf)