Nallatech, the leader in high-performance FPGA computing solutions, and Impulse Accelerated Technologies announced the availability of the Impulse C compiler for the Nallatech H100 series of FPGA accelerator products. Built with the goal of simplifying the design of scalable clusters, Nallatech’s H100 series delivers improved price/performance, increased performance density and reduced power consumption for high performance computing users across a range of market sectors including Financial Services, Geosciences and Bioinformatics. Customers can efficiently scale from a single FPGA processor to an architecture utilizing hundreds of FPGAs as part of an integrated solution targeting IBM Blade Centers.
The Impulse CoDeveloper tools provide users with a familiar, easy-to-use design environment for creating high-performance FPGA accelerator applications using ANSI-C. The Impulse tools allow FPGA algorithms to be developed and debugged using popular C/C++ development environments, including Microsoft Visual Studio(TM) and GCC-based tools. The CoDeveloper software-to-hardware compiler translates C-language processes to low-level FPGA-hardware, while optimizing the generated logic and identifying opportunities for parallelism. The compiler analyzes untimed C code and schedules multiple statements and operations into single-clock instruction stages. CoDeveloper unrolls loops and generates loop pipelines to exploit the extreme levels of parallelism possible in an FPGA.
Used in conjunction with the Nallatech H100 series C-to-Executable tool flow, customers wishing to exploit the benefits of FPGAs are able to create massively parallel applications targeting the latest FPGA hardware platforms from Nallatech.