CoValidator, from Impulse Accelerated Technologies, automatically generates FPGA test benches from C. CoValidator is an extension of the Impulse CoDeveloper C-to-FPGA tools. CoValidator with CoDeveloper enable FPGA system designers to write, refactor, optimize and synthesize FPGA software and hardware with ANSI C, then verify the results using industry-standard simulation tools.
CoValidator generates hardware test benches from the same C code used to describe and test algorithms in software, reducing test development time and increasing overall system reliability by having test development stay in step with design development.
CoValidator HDL Test Bench Generator Highlights
- Design your complex, streaming algorithms using Impulse C
- Validate correct untimed algorithm behavior with standard C compilers and debuggers such as Visual Studio, Eclipse, or GCC
- Refactor, optimize and compile your C code to create synthesis-ready HDL
- Verify the generated HDL using industry-standard RTL simulators, and using automatically generated HDL test benches, before synthesizing the HDL to a target FPGA device
CoValidator adds a fast path from C-language to hardware-accurate and bit-accurate RTL simulation. Impulse developers create complex image, signal and data processing FPGA hardware, and hardware test bench elements concurrently using standard C. Standard C debuggers such as Visual Studio can be used to validate applications. The C code is refactored, optimized and compiled to create synthesis-ready HDL.
With CoValidator, VHDL test benches are created automatically for ModelSim or other IEEE compliant VHDL simulators. Third-party and open source libraries can be used to generate streams of input data, for example using standard-format audio, image or video files. Development time is shorter, development costs are lower and results are better.
More info: Impulse Accelerated Technologies