SiliconBlue Technologies introduced two Wafer Level Chip Scale Package (WLCSP) options for their iCE65 mobileFPGA family. The ultra-low power, low cost features of iCE FPGAs combined with the die-sized packages in 0.5mm and 0.4mm ball pitch, provides solutions that meet the stringent size and space requirements of today’s real-world consumer mobile designs. Unit cost for the iCE65L04 (200,000 gates) in CS63 is $1.50US, and $3.00US for the iCE65L08 (400,000 gates) in CC72, both 1M unit quantities (2010). CS63 is now available in high volume and CC72 available in sample quantities.
With packaging done at the wafer level, the iCE65L04 and iCE65L08 WLCSPs eliminate expensive substrates and gold wire bonding. Both options offer mobile handheld designers new die-sized solutions at 3.2mm x 3.9mm with 0.4mm ball pitch and at 4.4mm x 4.8mm with 0.5mm ball pitch, respectively. The combination of high-density logic and ultra-small WLCSPs provides designers the ability to integrate up to 17x more logic functionality into the same board space versus competing Flash FPGA/CPLDs.
Compared to standard surface-mount packaging, WLCSPs also provide reduced chip-to-PCB inductance and improved thermal dissipation. In addition, all package dimensions meet industry standard JEDEC/EIAJ pitches, making them directly compatible with today’s SMT assembly and test.
|Size||3.2mm x 3.9mm||4.4mm x 4.8mm|
|Gates||200K System Gates||400K System Gates|
|I/O||48 I/Os; 4 diff pairs||55 I/Os; 8 diff pairs|
|Power||Icc0sleep = 5µA Operating Icc= 15µA @ 32KHz||Icc0sleep = 11µA Operating Icc = 30µA @ 32KHz|
More info: SiliconBlue iCE65 Ultra Low-Power Programmable Logic Family (pdf)