Synopsys Synphony HLS (High Level Synthesis) now supports Xilinx Virtex-6 FPGAs. The high level synthesis flow provides Virtex-6 FPGA users with more automatic target-specific optimizations and architecture exploration from high level models and delivers up to 10X higher design and verification productivity than traditional RTL flows for communications and multimedia applications. Synphony HLS and C-model generation is available now for FPGA and ASIC design flows. Synphony HLS is integrated with the MATLAB and Simulink from The MathWorks. The reference design is available upon request to Synphony HLS customers.
Synphony HLS generates optimized RTL for Virtex-6 FPGA implementation as well as testbench scripts to verify that the RTL implementation behaves exactly as the original model. Synphony HLS also generates fixed-point C-models that can be used for system validation and functional verification. These features enable engineering teams to more rapidly create new designs or upgrade existing designs to Virtex-6 FPGAs.
The Synphony HLS product synthesizes architecturally optimized RTL from high level models built from the Synphony HLS-optimized IP libraries. The high level synthesis engine also optimizes for the target FPGA technology by offering an advanced timing mode which accurately characterizes operations on the Virtex-6 FPGA device using the Synopsys Synplify Pro and Synplify Premier logic synthesis tools. This feature enhances mapping to the Virtex-6 FPGA’s on-chip resources such as hardware multipliers, accumulators and memories, improves the overall optimization results and provides faster timing closure for Virtex-6 FPGAs.
Using the Synphony HLS product, engineers can create and explore algorithm implementation architectures much earlier in their projects. Designers can provide constraints that specify the architectural transformations and optimizations that the Synphony HLS engine will use to generate RTL, RTL testbench scripts and C-models that can be used in a variety of system simulation environments and virtual prototypes. This high level synthesis methodology allows designers to stay in their preferred algorithm modeling environment, eliminating the need to re-code and re-verify models and enabling early system-level validation and verification.
A Synphony HLS reference design is now available which demonstrates the Synphony HLS flow into the Avnet Xilinx Virtex-6 FPGA DSP kit. The application is a digital up converter (DUC) and a digital down converter (DDC) for cellular basestations. The kit includes the Synphony high level model, MATLAB scripts for verification, and a suite of high level synthesis results showing architectural exploration on Virtex-6 devices. It also includes implementations that map to the Virtex-6 ML605 FPGA board and run in real-time. The reference design will allow teams to be up and running with the Synphony HLS software and Virtex-6 FPGAs within hours.