MAZeT announced the EnDat-IP for customized applications. The IP core has been certified by Heidenhain (the originator for the EnDat master) for implementation in FPGAs and ASICs. The serial communication interface for rotary and linear distance measuring systems was developed by MAZeT. The EnDat-IP has been used to date in a diverse range of technologies and application-specific modifications including safety-relevant applications.
The FPGA soft-macro of the EnDat interface describes the control side part (master component) of the interface between an absolute position encoder (encoder) from Heidenhain and a user’s subsequent electronics (control). The EnDat interface master component is intended for implementation in different types of FPGA families as an FPGA soft-macro (FPGA-EDIF netlist). With a large scope of available functions, the FPGA soft-macro ensures that a given total package of control tasks will be effectively distributed onto the EnDat master component and a microcontroller.
FPGA Softmacro for EnDat Features
- Implements EnDat 2.2 command set
- Implements EnDat 2.1 command set
- Supports SSI interface
- Functionality tested with Heidenhain encoders
- Supports up to 16 MHz clock rate for EnDat interface (at 100 MHz system clock)
- Propagation times of cable determination and compensation
- Allows cyclic position value queries through continuously available clock
- Performs CRC evaluation
- Data access via 6-bit address bus and 16-bit data bus for 8-bit and 16-bit microcontroller
- Access via hardware / software and timer strobe
- Additional functions of SAFETY master
- Two parallel interfaces for redundant data transfer of position 1 and position 2 including error bits
- Predefined 4-fold cycle for reading of monitoring functions (generation of position 1 and position 2)
- Internal compariso n of Pos1 and Pos2
- Additional monitoring functions
More info: MAZeT
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