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Apical Smart Backlight Display System

Posted by Ken Cheung in FPGA-based Product,Reference Design on Thursday, January 8, 2009

Apical Limited and Xilinx, Inc. (Nasdaq: XLNX) introduced the Apical Smart Backlight Display System. The new technology reduces power consumption and enhances the viewing experience on HDTVs. The Smart Backlight imaging solution combines the Apical iridix image processing technology with Xilinx Spartan-3 field programmable gate arrays (FPGA) to deliver over 50% total device power savings and improve image clarity for mid-to large LCD panel applications. HDTV product developers can immediately begin designing with the new Apical Smart Backlight display technology. A complete reference design is available from Apical and Avnet. In addition, a mezzanine development board suitable for evaluation and system integration may be obtained from Avnet Design Services.

The Smart Backlight system takes advantage of the low power capabilities of Spartan-3A and Spartan-3E FPGAs to support the use of ‘eco’ modes in HDTV products and lower overall operating costs. Maximum power savings can be as much as 75%, significantly greater than other power reduction techniques such as adaptive backlighting. In addition, the iridix processing engine implemented on Spartan-3 devices enables Smart Backlight displays to respond to changes in ambient conditions, such as sunlight. Its advanced algorithms model the ability of the human eye to perfectly adapt video images, even in bright viewing environments, in order to adjust power consumption and dynamically correct color and contrast.

Reduction in power consumption is a critical requirement in the HDTV market, but product developers still need to differentiate on image quality. Apical has developed an approach to doing both with its Smart Backlight system and iridix processing technology. The programmable platforms enable developers to capitalize on the competitive advantages in a highly cost-effective way without any compromises in performance or capabilities, which is not the case with standard chipset designs and more rigid ASIC alternatives.

More info: Apical | Xilinx

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