SynaptiCAD Debuts New Version of IO Checker FPGA Verification Tool

HDL Work IO Checker ~ SynaptiCAD

SynaptiCAD announced a new version of HDL Work’s IO Checker. The tool verifies that signal names used in the FPGA are connected to the appropriate signals on the PCB. IO Checker v2.2 pricing varies between $945 and $6615 based on the number of FPGA vendors supported and the pin limit. The new version of IO Checker is available for download now.

IO Checker verifies the voltage values connected to the FPGA power and reference pins. The tool uses rules (based on regular expressions) to match the signals names in both the FPGA and PCB design environment. The rules can be generated automatically and be fine-tuned by the designer. This automated approach will often match 80% to 90% of all device pins.

The flexibility of HDL Work IO Checker can be used in any design flow and does not require any design methodology. The rules generator in combination with the sorted “problem view” allows engineers to validate a 1000+ pins device in about 30 minutes.

IO Checker 2.2 Features

  • Alternate device migration
  • Improved power and ground checks
  • Search widgets
  • Xilinx Vivado pin reader
  • New Device support:
    • Altera: Cyclone V, Arria V, Stratix V FPGA
    • Xilinx: Artix-7, Kintex-7, Virtex-7, Zynq FPGA

More info: SynaptiCAD IO Checker