HDL Designer with SystemVerilog Support

Mentor Graphics Corporation (NASDAQ:MENT) announced last month that it has added SystemVerilog support to their HDL Designer(TM) tool. HDL Designer Series product is used to accelerate register transfer level (RTL) design reuse and optimize design creation, synthesis, and verification processes for complex application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA) designs. The HDL Designer Series product formulates an optimum design-to-verification environment for creating and managing complex designs using VHDL, C/C++, PSL, Verilog, mixed-languages, and SystemVerilog.

HDL Designer Series with SystemVerilog help lower the barrier to entry for hardware design and verification engineers by providing a unified environment for all HDLs, while taming the complexity of object-oriented programming. As a result, the HDL Designer Series product can significantly improve designer productivity by accelerating and optimizing design time by automatically evaluating RTL code quality, design integrity and analysis, and design visualization for effective design reuse.

HDL Designer supports the following SystemVerilog features:

  • Mixed-language and dialect support
  • Assertions and coverage reports
  • Auto detects, dialect, and top-of-design
  • The ability to instance SV1800 components with V95-compatible port descriptions in V95 BD/IBD to create structural design
  • Where Used and Where Bound reports
  • Cross-highlighting
  • Additional Browser Objects: SystemVerilog packages, program blocks, interfaces, and classes
  • Hierarchy Browser additions: program blocks, interfaces, and class instances
  • File templates for new objects, such as packages and classes
  • Updated viewpoint options

The HDL Designer product is seamlessly integrated with other Mentor Graphics ASIC flows, FPGA flows and supporting applications, including: simulation, formal verification, hardware-assisted emulation, synthesis, and place-and-route (P&R) environments, resulting in quality reuse and design portability.

In addition, HDL Designer generates documentation for design reviews, communications between design groups, and establishing an archival system for future reuse. Within minutes, designers can create an interactive website to describe designs both textually and graphically for effective design development and communications.

HDL Designer can:

  • Manage and help you understand code, including object oriented relationships
  • Assist in the implementation of new language features and constructs
  • Quickly trace dependencies, file-class-object-instance relationships and more
  • Summarize and quantify code characteristics
  • Automate and simplify data management
  • Design, measure and document for practical code reuse
  • Assist in the integration of VHDL, Verilog and SystemVerilog Code

The HDL Designer solution with SystemVerilog is available now, with pricing starting at $6,900 (USD).

More info: HDL Designer Series with SystemVerilog Support