Aldec HES Platform Features Mirror-Box Debugging Technology

Aldec’s Hardware-Assisted Simulation (HES) platform now features Mirror-Box debugging technology. Mirror-Box debugging technology streamlines debugging during hardware-assisted simulation. The Mirror-Box technology enables any component, at any hierarchical level, to be mirrored so that two implementations of the same component can be simulated: one implementation is the original RTL code which resides in the HDL Simulator and the other is its FPGA counterpart which resides in the hardware board.

Aldec Hardware-Assisted Simulation (HES) platform with Mirror-Box debugging technology

Mirror-Box Features

  • Helps verification engineers reduce verification cycles
  • Streamlines debugging during hardware-assisted simulation
  • Allows any component, at any hierarchical level, to be mirrored
  • Generates two implementations of instance selected as Mirror-Box
  • Mirrored instance resides in FPGA hardware
  • Mirror Box resides in HDL simulator
  • Mirror Box output checker in simulator provides run-time outputs comparison
  • Additional multiplexer in FPGA allows switching active driver between Simulator and FPGA implementations
  • Verification engineer can switch between HDL and FPGA without rerunning Synthesis and Place and Route
  • Eliminates the need to rebuild the FPGA several times during debugging
  • Runtime comparison of component outputs between RTL code and actual hardware
  • Quick modification of the HDL code for debugging while rest of DUT resides in the FPGA
  • Rebuilds FPGA only for complete regressions
  • Discovers hardware implementation defects in simulation environment
  • Automatic generation of assertion code to compare FPGA and simulation model

More info: Aldec