Synopsys HAPS-70 FPGA-based Prototyping System Features Xilinx Virtex-7
Synopsys introduced the HAPS-70 Series FPGA-based prototyping systems for system-on-chip (SoC) designs. The HAPS-70 FPGA-based prototyping systems are available now in nine model variants. Capacities range from 12 to 144 million ASIC gates. The series consists of the HAPS-70 S12, HAPS-70 S24, HAPS-70 S36, HAPS-70 S48, HAPS-70 S60, HAPS-70 S72, HAPS-70 S96, HAPS-70 S120 and HAPS-70 S144. The S denotes ASIC Gate count support.
The Synopsys HAPS-70 Series features the latest generation Xilinx Virtex-7 FPGA devices to support a wide range of design sizes with capacities from 12 to 144 million ASIC gates. The flexibility and matched pin connections between the Virtex-7′s I/O banks and HapsTrak 3 connectors enable HAPS users to utilize I/O bandwidth where it is needed most while minimizing the number of unused pins.
HAPS-70 systems are integrated with an intelligent prototyping software environment that enables faster partitioning and automates the creation and debug of prototypes for a range of designs from individual IP blocks and processor sub-systems to complete SoCs, easing the path from RTL to operational prototype. The modular architecture of the HAPS-70 systems enables engineers to use a common prototyping environment for IP and SoC software development, hardware/software integration and system validation, reducing duplication of effort across projects.
New “HAPS-aware” features of Synopsys’ Certify multi-FPGA prototyping software increase prototyping productivity by up to 10x with patent-pending algorithms to automate logic partitioning and live hardware queries to ease system bring-up compared to manual partitioning methods. The new prototyping systems also support HAPS Deep Trace Debug for greater debugging efficiency, providing approximately 100 times more signal storage capacity than the traditional memory storage employed by on-chip FPGA logic debuggers.
Synopsys HAPS-70 Features
- Modular system architecture scales from 12-144M ASIC gates to accommodate a range of design sizes, from individual IP blocks to processor sub-systems to complete SoCs
- Enhanced HapsTrak 3 I/O connector technology with high speed time-domain multiplexing delivers up to 3x performance improvement in data throughput over traditional pin multiplexing
- System definition and bring-up utilities speed hardware assembly and ensure the prototype’s electro-mechanical integrity
- Advanced power and cooling management
- Design planning tools reduces time-to-prototype by 2-3 months streamlining the transition from block level IP validation to full system integration
- Improve debug efficiency with 100x greater visibility and 8x faster download time of debug trace buffer data
- Advanced use modes including co-simulation, transaction-based verification, and hybrid prototyping
- HAPS-70 FPGA-based prototyping systems are available in nine model variants, with capacities from 12 to 144 million ASIC gates
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