Jointwave H.264 Encoder IP Cores

Jointwave introduced their H.264 series encoder IP core. The Jointwave IP cores support Level 1.0 to 5.1 of H.264 (MPEG-4 Part 10, also called AVC). The cores cover baseline profile, main profile, and high 4:2:2/4:4:4 profile. Compare to competitors’ solutions, Jointwave’s IP core uses less hardware resources. The H.264 encoder features ultra-low frequency, super low latency, small die size, and ultra-low power consumption. Jointwave H.264 IP core can be used without embedded or external CPU, and reduce the system complexity. It runs on FPGA and ASIC.

Jointwave H.264 IP is now available. Delivery includes RTL code for ASIC and netlist for FPGA. Lowest cost evaluation and demo boards are available on the following platforms:

  • Altera Cyclone III development kit, $995
  • Altera Stratix III development kit, $2,450

Platforms that will be available soon:

  • Xilinx Spartan-3 development kit,$1,595
  • Xilinx Virtex-6 development kit, $2,495
  • Xilinx Spartan-6 development kit, $495

Jointwave H.264 Encoder IP Cores Features

  • Full searching algorithm in both full pixel and 1/4 sub-pixel motion estimation, to get best objective and subjective video quality
  • Bit rate is 40% of MPEG2 for equal quality
  • Configurable search range
    • Horizontal: +/-61.75 ~ +/-21.75
    • Vertical: +/-29.75 ~ +/-16.75
  • Multiple reference frames (maximum 2)
  • Skip mode for P frame, Direct8x8 and Direct16x16 for B frame
  • Multiple inter prediction modes: 16×16, 16×8, 8×16, 8×8
  • I16x16 and I4x4 all intra prediction modes
  • Configurable GOP pattern: I only, IPP…, IBPBP…, IBBPBBP…
  • Configurable GOP sequence length
  • Exceedingly fast CABAC module, encodes 1 binarized bit per cycle. Capable of outputting 100Mbps when run at 300MHz
  • VBR and CBR, rate control for both CAVLC and CABAC
  • Real-time encoding, Very low latency
  • 1/4 sub-pixel motion estimation
  • Mode decision in 1/4 sub-pixel to get best quality
  • Hadamard transform for both intra and inter prediction
  • Deblocking filter
  • Integrated SD/DDR controller, or shares SD/DDR through AHB with CPU and other parts on SOC
  • Standalone solution, no extra CPU or software required
  • Fully synthesizable, gate level simulation verified
  • FPGA Proven
  • One 1920×1088@30~60fps or 6~12 D1 high quality H.264 encoders can be put in one FPGA
  • Maximum 600Mhz on 90nm process
  • Maximum 480Mhz on 130nm process
  • Maximum 300Mhz on high-end FPGA, e.g. StratixIIII, Virtex5
  • Maximum 1080p@60fps on Virtex5 and StratixIIII
  • Ultra low power consumption, 82mw for 1080p@60fps on 45nm process, 98mw for 1080p@30fps on 90nm process, 20mw for 720p@30fps on 65nm process

More info: Jointwave