Altera has completed interoperability testing between their Stratix IV GT FPGA and the MoSys Bandwidth Engine device in a serial memory application. Stratix IV GT FPGA devices leverage the GigaChip Interface to interoperate with MoSys’s Bandwidth Engine device. Altera is the first FPGA vendor to deliver device support for the GigaChip Interface. The interoperability gives 100G wireline application designers a high-performance, high-bandwidth memory solution.
The GigaChip Interface is a short-reach, low-power serial interface. It enables highly efficient, high-bandwidth, low-latency performance. Stratix IV GT FPGA devices support the GigaChip Interface through the device’s soft memory controller, which provide maximum design flexibility, and the device’s 11.3 Gbps transceivers. Thanks to GigaChip Interface support, Stratix IV GT FPGAs enables engineers to increase system performance, while minimizing board costs and pin counts.
The GigaChip Interface represents a bandwidth density performance increase of 4X over DDR-type interfaces. It also reduces system power and interface costs by 2X to 3X. The GigaChip Interface leverages transceiver technology to increase chip-to-chip communications performance. MoSys utilized the Stratix IV GT FPGA in the development of the GigaChip Interface as a result of the timely availability of Altera’s high-performance transceiver technology.
Stratix IV GT FPGAs are currently shipping in volume production. MoSys’s Bandwidth Engine devices are sampling now.