The latest versions of GateRocket’s RocketDrive FPGA verification and debug solution will roll out in July 2010. RocketDrive reduces verification and debug time by integrating the FPGA into the HDL simulator to provide a “hardware in the loop” process based on GateRocket’s Device Native methodology. This technique combines the actual FPGA hardware and RTL simulation models in the same verification run and allows execution of the design on the target FPGA device. The new version features support for Xilinx Virtex-6 programmable devices. Pricing starts at $25,000.
The new Virtex-6 RocketDrives use the largest LX and SX devices for advanced logic and DSP applications respectively. GateRocket also offers a cost effective mid-range device configuration targeted at users who do not require the largest FPGA device in the family. By using devices optimized for specific needs, GateRocket can pass along the cost savings for an even greater return on investment. Each RocketDrive configuration offers the same enhanced verification performance and debug efficiency, and maintains complete compatibility with popular EDA logic simulators from Cadence, Mentor and Synopsys.
The GateRocket solution enables designers using Virtex-6 devices to move smoothly between RTL and the specific FPGA being targeted, combining actual FPGA hardware and RTL simulation models together in a single verification run, without changes in the design flow or methodology. This technique, called soft patch, provides engineers with the ability to make a change to one or more RTL blocks and re-run them along with the hardware implementations of the other blocks, thereby avoiding the need to rebuild the device for each fix and enabling multiple design-change-debug iterations in a single day. The net result is a time savings of up to 50% or more over traditional verification and debug approaches.
More info: GateRocket