Xilinx Virtex-5 SX240T FPGA and Floating Point Operator IP Core v4

Xilinx, Inc. (Nasdaq: XLNX) introduced the Virtex(R)-5 SX240T FPGA device and version v4.0 of the Floating-Point Operator (FPO) IP core. The SXT240T is the latest member of the 65nm Virtex-5 SXT FPGA platform, which is optimized for high-performance digital signal processing (DSP). With up to 528 GMACs of multiply-and-accumulate performance and over 190 GFLOPS of single-precision, floating-point DSP performance, the new device offers developers of broadcast video, medical imaging, wireless communication, defense, and high-performance computing applications the world’s highest performing reconfigurable DSP solution.

Customers can start designing the SXT240T into their next generation products today using the new ISE(R) Design Suite 10.1.01. Initial samples of the device will be available in the third quarter of 2008, with full production expected to begin in the fourth quarter. The Floating-Point Operator IP core V4.0 is provided at no additional cost to customers as part of the standard IP library in the Core Generator system included with ISE Design Suite 10.1.01.

The new 65nm Virtex-5 SXT240T device incorporates 1056 25bit x 18bit DSP48E slices that designers can combine to implement scalable signal processing chains using dedicated routing resources. Each DSP48E slice consumes typically 1.4mW/100MHz dynamic power enabling efficient power management without sacrificing performance. In addition, the SX240T device has over 18Mbits of block RAM to store data and coefficients, and 24 high-speed GTP serial transceivers each supporting data rates of up to 3.75Gbps. The higher DSP bandwidth combined with memory and high speed serial connectivity enables designers to use fewer devices on their printed circuit boards, thus reducing overall system costs and power consumption while meeting stringent performance requirements.

The new FPO IP core has been optimized to use the 25bit x 18bit DSP slices to perform a floating-point multiply operations with half the resources of previous versions. The SXT240T device and the FPO IP core combine to deliver over 190 GFLOPS of single-precision, floating-point DSP performance for high-performance computing, medical imaging and defense applications. This amount of DSP performance can be used to implement up to 63 percent more single-precision floating-point multiply operations or 125 percent single-precision floating-point add operations than competing devices.

DSP designs can be created for the SXT240T device using the XtremeDSP Solution Development Tools Package that includes System Generator for DSP and the AccelDSP(TM) synthesis tool. These tools provide an FPGA implementation path for DSP algorithms developed using The Mathworks popular MATLAB(R) and Simulink(R) DSP modeling environments. System Generator for DSP provides a Xilinx optimized DSP blockset, netlist generation and hardware-in-the-loop co-simulation plug-ins for the Simulink environment. The AccelDSP synthesis tool extends these capabilities to also include fixed-point conversion, design exploration and RTL generation of floating-point MATLAB algorithms.

More info: Xilinx Virtex-5 FPGAs