Altera is hosting a series of FPGA related seminars in September. The training will take place in cities across the US and Canada. The classes are:
- Designing with an ARM-based SoC
- Developing Software for an ARM-based SoC
- Parallel Computing with OpenCL Workshop
- Advanced Timing Analysis with TimeQuest
- Timing Closure with the Quartus II Software
- Introduction to the Qsys System Integration Tool
- Advanced Qsys System Integration Tool Methodologies
Altera FPGA Seminars
Designing with an ARM-based SoC
This course is intended for hardware and firmware engineers and will leverage your knowledge of Qsys system design to guide you on implementing an Altera SoC with the ARM Cortex A9 hard processing system (HPS). This course focuses on the hardware aspects of using the processor in the SoC from the design, verification and debug hardware perspectives just as if the processor was external. Our intention is that you feel completely comfortable using the HPS in the SoC and know all of the resources at your disposal to work with the board designer, FPGA engineer, firmware engineer or software engineer to get up and running quickly.
Developing Software for an ARM-based SoC
This course is for firmware and low level software engineers and is intended to teach you about software bring up and development on the embedded ARM Cortex A9 hard processor system (HPS) in an SoC. The course isn’t intended to teach you software application or driver development, but rather concentrates on the unique aspects of the embedded HPS software flow in an SoC. You’ll learn everything you need to know to get started developing our software for the HPS component right away, where to go to get help, as well as how to use the Altera edition of the ARM DS-5 adaptive debugging tools at your disposal to debug your software.
Parallel Computing with OpenCL Workshop
OpenCL is a standard for writing parallel programs for heterogeneous systems. In the FPGA environment, OpenCL constructs are synthesized into custom logic. This course introduces the basic concepts of parallel computing. It covers the constructs of the OpenCL standard & Altera flow that automatically converts kernel C code into hardware that interacts with the host. In hands-on labs, you’ll write programs to run on both the CPU & FPGA. Note – the price for this workshop in Europe is $660. Note – this hands-on workshop provides an introduction to OpenCL for FPGAs. For in-depth training on OpenCL & Altera’s OpenCL for FPGAs solution attend the “OpenCL for Altera FPGAs” class from our partner, Acceleware.
Advanced Timing Analysis with TimeQuest
Using the Quartus II software version 13.0 and building upon your basic understanding of creating Synopsys Design Constraint (SDC) timing constraints, this class will guide you towards understanding, in more depth, timing exceptions. You will learn how to apply timing constraints to more advanced interfaces such as source synchronous single-data rate (SDR), double-data rate (DDR) and LVDS, as well as clock and data feedback systems. You will discover how to write timing constraints directly into an SDC file rather than using the GUI and then enhance the constraint file using TCL constructs. You will also perform timing analysis through the use of TCL scripts.
Timing Closure with the Quartus II Software
One of the greatest and most frustrating FPGA design challenges is closing timing. It is very common to find, after performing a complete timing analysis on an FPGA design, that one or more timing reports indicate a timing failure. How can this be corrected? The answer is not always obvious. This class teaches the techniques used by Altera Design Specialists to close timing on designs that “push the envelope” of performance. Example techniques include thoroughly analyzing the design for common timing failures, adjusting settings and assignments according to tool recommendations, selecting the correct clock resources and writing HDL code for optimal performance.
Introduction to the Qsys System Integration Tool
This class will teach you how to quickly build designs for Altera FPGAs using Altera’s Qsys system-level integration tool. You will become proficient with Qsys and expand your knowledge of the Quartus II FPGA design software v. 13.0. You will learn how to quickly integrate IP and custom logic into a system and how to optimize designs for performance. Since Qsys makes design reuse easy through standard interfaces, we will dive deeply into the Avalon-Memory Mapped and Streaming Interfaces as well as learn about the Amba AXI interfaces. The class provides a significant hands-on component, where you will gain exposure to tool usage as well as system and custom HDL component design.
Advanced Qsys System Integration Tool Methodologies
In this class, you will learn advanced features of Altera’s Qsys system level integration tool and expand your knowledge of the Quartus II FPGA design software v. 13.0. You will learn how to simulate Qsys systems in ModelSim-Altera using Avalon bus functional simulation models, exercise and monitor system behavior with the System Console, and build hierarchical Qsys systems. You will also learn how to build custom components using Tcl. The class provides a significant hands-on component, where you will gain exposure to tool usage as well as system design.