Altera and Flexibilis developed a High-availability Seamless Redundancy (HSR) and Parallel Redundancy Protocol (PRP) reference design. It features Flexibilis Redundant Switch (FRS) intellectual property (IP) implemented on an Altera low-power, low-cost Cyclone-class FPGA or Cyclone V SoC. The reference design simplifies development and implementation of highly reliable mission-critical communications systems in smart grid substation automation equipment.
The new reference design makes it easy to implement an FPGA-based HSR/PRP Ethernet switch. It combines Altera FPGA devices with a FRS IP to provide an easy and cost-effective way to implement highly reliable mission-critical communications systems in smart grid substations by offering no license negotiation, no up-front licensing costs and no per-unit royalty reporting.
The Flexibilis HSR/PRP IP included in the reference design is a triple-speed 10/100/1000 Mbps Ethernet Layer 2 switch that is scalable from 3 to 8 ports and is compliant with the IEC 62439-3 standard. The IP is optimized for use on an Altera low-power, low-cost Cyclone IV FPGA, Cyclone V FPGA or Cyclone V SoC, which feature an integrated dual-core ARM Cortex-A9 processor subsystem.
Cyclone V SoCs enable designers to reduce component costs by implementing their HSR/PRP switch along with the associated software stacks running on the ARM processor subsystem in the FPGA. For timing synchronization, the HSR/PRP solution supports IEEE 1588 Precision Time Protocol (PTP) Version 2.