Actel Libero Features Access to Over 50 IP Cores

Actel’s Libero Gold and Platinum editions now include access to over fifty IP cores. The Libero Gold Edition, which supports Actel FPGAs up to 1.5 million system gates, includes obfuscated versions of the Actel IP cores that can be easily used in designs but cannot be modified. The Libero Platinum edition supports Actel FPGA devices above 1.5 million system gates, such as AGLE3000, M1AGLE3000, A3PE3000, M1A3PE3000, A3PE3000L, RT3PE3000L, RTAX2000S, RTAX4000S, RTAX2000D, RTAX4000D, and AX2000.

RTL source code for Actel IP cores can be accessed through Actel’s SmartDesign tool:

  • CoreAHB
  • CoreAHB2APB
  • CoreAHBLITE
  • CoreAHBNVM
  • CoreAHBSRAM
  • CoreAI
  • CoreAPB
  • CoreFROM
  • CoreGPIO
  • CoreINTERRUPT
  • CoreMEMCTRL
  • CoreMBX
  • CoreMP7BRIDGE
  • CoreREMAP
  • CoreAHB
  • CoreAHB2APB
  • CoreAHBLITE
  • CoreQEI
  • CoreAHBNVM
  • CoreAHBSRAM
  • CoreAI
  • CoreAPB
  • CoreFROM
  • CoreGPIO
  • CoreINTERRUPT
  • CoreMEMCTRL CoreMBX
  • CoreMP7BRIDGE
  • CoreREMAP
  • CoreTIMER
  • CoreUARTAPB
  • CoreWATCHDOG
  • Core16550
  • Core3DES
  • Core8051s
  • CoreAES128
  • CoreDES
  • Core3DES
  • CoreAI
  • CoreAPB
  • CoreCFI
  • CoreDDR
  • CoreFMEE
  • CoreI2C
  • CorePWM
  • CoreRSENC
  • CoreSDR
  • CoreSPI
  • CoreUART
  • CoreUART_APB
  • CoreABC
  • CoreLPC

More info: Actel