Altera Qsys System Integration Tool

Altera’s Qsys is a system-integration tool for FPGA designers. Qsys automatically generating interconnect logic to connect intellectual property (IP) functions and subsystems. Qsys features the industry’s first FPGA-optimized network-on-chip-based interconnect. Qsys offers memory-mapped and streaming interface support that achieves nearly double the performance of Altera’s SOPC Builder tool, while improving system scalability for large FPGA designs and enabling support for industry-standard interfaces (Avalon and AMBA AXI and AHB standards from ARM, etc). A beta release of Qsys is available in Quartus II Subscription Edition software v10.1

Qsys Highlights

  • Reduces time and effort in the FPGA design process
  • Powered by a new FPGA-optimized network-on-chip technology
  • Enables performance optimizations, and automatic insertions of pipeline registers
  • Interconnect can achieve nearly double the fMAX performance compared to SOPC Builder
  • Engineers control the aggressiveness of the automatic pipelining to make trade-off decisions between fMAX and latency
  • Supports hierarchical design for large systems
  • Allows designers to add additional systems to design with minimal impact to existing systems
  • Offers memory-mapped and streaming interface support
  • Supports Avalon, AMBA AXI and AHB standards
  • Automatically handles the bridging between multiple interface standards
  • Delivers performance improvements over conventional bus and switch fabric interconnections
  • Packetizes all memory-mapped and streaming data
  • Automatic pipelining feature to further increase system fMAX
  • Enables system scalability by dividing large FPGA designs into multiple sub-systems

More information: Altera