Barco Silex BA414E Public Key Crypto Engine IP Core

Barco Silex announced the BA414E Public Key Crypto Engine Intellectual Property (IP) core. The BA414E is based on a scalable, highly pipelined and optimized arithmetic unit. The BA414E PK Crypto Engine can be mapped to any existing FPGA technology and all ASIC processes with reconfigurable elementary DSP blocks. The BA414E IP does not require any assistance from the main CPU to handle the complete Public Key processing. Based on a cost-effective µ-coded sequencer (coupled to a µ-DMA), the core can support complex operations and algorithms like RSA, CRT, DSA and ECDSA (including pre- and post-processing).

Barco Silex BA414E Public Key Crypto Engine Intellectual Property (IP) core

BA414E PK Crypto Engine Intellectual Property Core

  • High-level of scalability: 1, 4, 16, 64 or 256 Multipliers
  • Portability: ASIC, Actel, Altera, Xilinx
  • Supports all arithmetic operations in both fields F(p) and F(2m)
    • Modular or normal Addition/Subtraction
    • Modular Multiplication/Division/Inversion
  • Supports arbitrary data/key sizes up to 4096 bits
  • Supports all standard PK crypto primitives
    • Modular Exponentiation (RSA)
    • Point Doubling/Addition/Multiplication for ECC-F(p) and F(2m)
  • Supports high-level PK Algorithms
    • RSA and CRT, Primality Test for Key Generation
    • Elliptic Curve Cryptography (ECC)
    • Digital Signature Algorithm (DSA) and Elliptic Curve DSA (ECDSA)
  • NIST recommended Curves are supported
    • Prime Field P-192, -224, -256, -384, -521
    • Binary Field K/B-163, -233, -283, -409, -571
  • Pre- and post-processing automatically executed by the core
  • Control Interface: APB-compliant / AXI4-lite
  • Data Interface: Generic Memory Interface with internal DMA
  • 100% CPU Offload solution
  • Off-the-shelf and silicon-proven solution
  • Optional add-on for protection against SPA/DPA
  • Data Sheet is available under NDA
  • ASIC 90nm (Tiny): < 30kgates, up to 500 1024-bit CRT op/sec
  • ASIC 90nm (Fast): Max Freq=500MHz, up to 5,000 1024-bit CRT op/sec
  • High-end FPGA: Max Freq=250MHz
  • Low-end FPGA: Max Freq=80MHz
  • Performances and complexity are available on request for any FPGA device (any config)
  • Netlist or RTL
  • Scripts for synthesis
  • Self-checking TestBench based on FIPS vectors

More info: Barco Silex