Synplicity®, Inc. (Nasdaq:SYNP) has enhanced its Premier software to provide more time-to-market benefits to designers using high-density FPGAs. In the latest release, Synplicity optimized their graph-based physical synthesis technology for Xilinx Virtex-5 FPGAs to deliver exceptional timing closure, analysis and debug of the devices. Synplicity also has extended the improvements to FPGA designers targeting Altera Stratix-III, Stratix-II and Stratix-II GX FPGAs, through the company’s Synplify Premier Beta Program. Synplify Premier 9.0 is available now. Pricing for the design environment starts at $54,000 (USD). Synplify Premier software customers who are on active maintenance will receive the 9.0 release at no extra cost.
Synplify Premier 9.0 gives users accurate timing information and insight into debug performance-related issues immediately following synthesis. Designers don’t have to go through the hours of place and route, typical in traditional flows, to get detailed timing information. Once the designer is happy with the results, placement from the Synplify Premier software is passed to place and route to ensure deterministic results and thus the fastest timing closure. In addition to providing an optimal solution for timing closure, Synplify Premier 9.0 provides several algorithmic QoR enhancements and productivity boosting features such as a new user interface, additional SystemVerilog constructs and a new module generation capability.
Synplicity continuously works to expand the breadth of its synthesis technology to provide the most robust platform for FPGA implementation and design. The Synplify Premier Platform is a complete environment offering a range of features including RTL analysis, source-level debug, HDL analysis, advanced floorplanning, physical analysis, module generators and optimizations for DSP design. The Synplify Premier solution is also a platform for implementation and debug of ASIC and SoC prototypes using a single FPGA.
Synplify Premier 9.0 offers additional features for improved productivity. For example, Synplicity has expanded its SynCore IP generator to support FIFOs in addition to RAMs. Designers supply parameters to indicate the size and type of RAM or FIFO and the IP generator wizard automatically creates technology independent RTL ready for synthesis into an FPGA. These features allow designers to avoid handwriting RTL or using technology dependent memory instantiations for these functions.
New SystemVerilog features in release 9.0 include:
- Array assignments (packed & unpacked)
- Port declarations for multiple dimensions
- Arrays as arguments to functions, tasks and modules
- Declarations in for-loop
- Argument by names
- Default argument types
Synplify Premier 9.0 is enhanced with algorithmic changes supporting the sophisticated architectural and routing structures for improved performance and area utilization reducing device cost. The huge capacity of 65-nanometer devices, coupled with new architectural features, complex routing and high-capacity memory structures can achieve even greater quality of results through the use of specialized synthesis tools with customized algorithms. Synplicity’s physical synthesis software features a unique direct-mapping technology employing a variety of sophisticated new heuristics tailored to minimize the number of logic elements used while still meeting timing objectives.
In order to fully address timing closure, designers must have highly accurate timing correlation between what a tool estimates and the final, actual timing. The only proven way to get this timing correlation is to perform detailed placement and routing during logic optimization and also to have access to FPGA-specific routing information (routing graph a.k.a. graph-based). Synplicity’s graph-based physical synthesis is the only product on the market that performs final detailed placement of logic during optimization, and therefore, is the only tool that successfully addresses timing closure. Actual testing on customer designs has shown that graph-based physical synthesis provides timing correlation within 10 percent of final post-route timing on over 90 percent of designs resulting in fewer design iterations, less time to completion, and logical and physical optimizations on the actual critical paths of the design.
Unlike other solutions, Synplicity’s patented graph-based physical synthesis technology merges logic optimization, placement and routing estimates into a single process which is used alongside a highly accurate interconnect timing graph (database) to help ensure a design’s critical paths use the fastest available routing resources in the target device. This is the only physical synthesis solution that creates detailed placement for all logic which is then passed on to the vendor tool for final routing.
As ASIC designers increasingly depend upon FPGAs to prototype all or part of their designs, there is a need for a synthesis and verification environment that can take HDL code written for an ASIC and efficiently implement it in an FPGA. The Synplify Premier platform accommodates this by performing automated gated-clock conversion handling of generated clocks and Synopsys DesignWare® components. Synplify Premier software addresses single FPGA prototypes, while Synplicity’s Certify® RTL prototyping product enables multiple FPGA prototypes with advanced partitioning and pin multiplexing technology.
More info: Synplicity’s Synplify Premier