FPGA News – 2007.11.15

Mentor Optimizes Flow Between Precision Synthesis, Simulink HDL Coder
Mentor Graphics Corporation (NASDAQ:MENT) announced support for hardware description language (HDL) generated by MathWorks Simulink HDL Coder in the Mentor Graphics Precision® suite of advanced synthesis products. This capability enables mutual customers to transfer VHDL and Verilog generated by Simulink HDL Coder into the Precision Synthesis tool directly to generate an optimized netlist implementation for field programmable gate array (FPGA) designs. All mutual customers using Precision 2006a release or newer with Simulink HDL Coder can benefit from this flow, which will improve the productivity of FPGA design synthesis.

World Markets for FPGA, DSP, and ASIC in Medical Imaging Equipment
Research and Markets has announced the addition of the new Frost & Sullivan Report “World Markets for FPGA DSP and ASIC in Medical Imaging Equipment” to their offering. This Frost & Sullivan research service discusses the trends and provides the market analysis of FPGA, DSP, and ASIC in the medical imaging equipment market. The research also discusses market dynamics that include industry challenges, market drivers and restraints, key market and technology trends, and competitive analysis of FPGA, DSP, and ASIC in the medical imaging equipment market. Based on the interplay of identified challenges, drivers, and restraints, unit shipment and revenue forecasts and unit shipment forecasts by application and package type are provided. In this research, Frost & Sullivan’s expert analyst thoroughly examines the following markets: X-rays, computed tomography, magnetic resonance imaging, positron emission tomography including PET/CT and single photon emission computed tomography, and ultrasound.

Actel Improves Libero IDE with Verific’s Front-end Software
p>Verific Design Automation said that Actel Corporation (Nasdaq: ACTL) has integrated its Verilog and VHDL parsers, analyzers and elaborators to serve as the front end to the Libero(TM) Integrated Design Environment (IDE). The recently introduced version of Actel’s Libero IDE was enhanced to ease the system-level design process for all of its field-programmable gate arrays (FPGAs). Its SmartDesign design entry capability lets designers move to a higher level of abstraction, reducing FPGA design and development time, improving productivity and speeding time to market. Through a tight integration with Verific’s front-end software, designers are able to create and automatically abstract block-based system designs into synthesis-ready VHDL or Verilog components.

Atmel Introduces CAP Starter Kit for Customizable Microcontroller
Atmel® Corporation (Nasdaq: ATML) announced the launch of the AT91CAP9A-STK Starter Kit for its CAP(TM) Customizable Microcontroller product family. The CAP Starter Kit is the ideal vehicle for low-cost, no-risk evaluation of the customization capabilities of the CAP MCU by mapping application-specific IP blocks into its FPGA that emulates the functionality of the CAP’s embedded Metal Programmable (MP) Block.