Xilinx Inc. (Nasdaq: XLNX) is at the DesignCon 2008 conference this week. Xilinx’s participation includes an FPGA industry business forum panel, DesignVision awards, high-speed serial backplane conference session, and a Virtex(TM)-5 FPGA enabled cell broadband demonstration.
Executive Views on the Turbulent FPGA Landscape
Tuesday, February 5, 10:15-11:45 a.m
Bruce Tally, vice president and general manager of Xilinx’s Design Software Division, joins a panel discussion examining key FPGA industry trends, including vendor independence, tool interoperability, and next generation technology.
Tuesday, February 5, 12:00 p.m.
Xilinx(R) ISE(TM) software and MOST(R) NIC LogiCORE(TM) IP Solution are DesignVision Awards finalists. Winners will be announced in the main theater.
A Design of Experiments for Gigabit Serial Backplane Channels
Thursday, February 7,10:40-11:20 a.m.
Jack Carrel, system I/O specialist at Xilinx, Bill Dempsey, president at Red Wire Enterprises, and Mike Resso, signal integrity expert at Agilent Technologies, will examine the challenges facing today’s high-speed serial backplane designers. Tradeoffs between signal integrity performance, cost, and reliability must be made to achieve the proper architecture for a robust physical-layer channel. The right combination of connectors, dielectric materials, and topology must be used to accomplish this engineering task. In this session, presenters will provide an in-depth look at the design of experiments using combinations of three high-speed connectors, three dielectric materials, and three channel lengths. Results of data analyzed with a 12-port vector network analyzer will be presented in time domain, frequency domain, and eye diagram domain.
IBM demonstrates a Cell Broadband Engine(TM) (Cell BE) connected to a Virtex-5 FPGA via FlexIO(TM) interface. This is the first and fastest coherent/non-coherent interface between the Cell BE processor and an FPGA. The Cell BE processor interfaces to RocketIO(TM) GTP transceivers at 3 Gbps resulting in a transfer bandwidth of 3 Gbps per FlexIO byte lane. This architecture can enhance the use of Cell BE processors for custom I/O interfacing, offloading specific tasks or interconnecting multiple processors. Visit Rambus/IBM at booth #205 for a demo and more information.