Xilinx ISE Design Suite 12

Xilinx announced version 12 of the ISE Design Suite. The latest version of the ISE design tools feature intelligent clock-gating technology that reduces dynamic power consumption by as much as 30%. ISE Design Suite 12 includes timing-driven design preservation, AMBA 4 AXI4-compliant IP support for plug-and-play design, and an intuitive design flow with fourth-generation partial reconfiguration capabilities that lowers system cost for a broad range of high performance applications. ISE Design Suite 12 is now available for all ISE Editions. List price starts at US$2,995 for the Logic Edition.

ISE Design Suite 12 innovations will rollout in phases with intelligent clock gating for Virtex-6 FPGA designs shipping now with the 12.1 release, partial reconfiguration for Virtex-6 FPGA designs starting in the 12.2 release, and AXI4 IP support to follow in the 12.3 release. The ISE 12 suite works with the latest simulation and synthesis software from Aldec, Cadence Design Systems, Mentor Graphics, and Synopsys.

Xilinx ISE Design Suite 12 Highlights

  • Full production support for all Xilinx Virtex-6 and Spartan-6 FPGA families
  • Interoperable design flows and tool configurations for logic, digital signal processing (DSP), embedded processing, and system-level design
  • Improved run time, streamlined system integration, and expanded IP interoperability across latest generation device families and Targeted Design Platforms
  • Intelligent clock-gating technology with fully automated analysis and fine-grain (logic slice) optimization capabilities
  • Reduces the number of transitions (a primary contributing factor of dynamic power dissipation in digital designs)
  • Analyzes designs using a series of algorithms to detect sequential elements (‘transitions’) within each FPGA logic slice that do not change downstream logic and interconnect when toggled
  • Software generates clock-enable logic that automatically shuts down the unnecessary activity at the logic slice level to accumulate power savings without having to shut off an entire clock network
  • Advanced design preservation capabilities
  • Designers can partition designs to focus on achieving required timing for critical blocks
  • Can lock blocks to preserve placement and routing while designers work on the rest of the design
  • Standardized IP interfaces on the open ABMA 4 AXI4 interconnect protocol
  • Support for fourth generation ‘on-the-fly’ partial reconfiguration technology
  • Developers of wired Optical Transport Network (OTN) solutions can implement a 40G multi-port muxponder interface with one-third fewer resources as compared to devices without partial reconfiguration
  • 2X faster logic synthesis and 1.3X faster implementation run times for large designs than previous versions

More info: Xilinx