Altera RapidIO MegaCore Function IP Core

Altera introduced their RapidIO MegaCore Function IP core. It is implemented in a Stratix IV GX FPGA with a Serial RapidIO Gen 2 switch from Integrated Device Technology (IDT). The IP core is the first Serial RapidIO Gen2 FPGA-based solution. The RapidIO MegaCore Function IP core is available now for download. It is available as encrypted IP or as source code for complete user control.

Altera RapidIO MegaCore Function IP Core Features

  • Compliant with RapidIO Trade Association, RapidIO Interconnect Specification, Revision 2.1
  • Successfully passed RIOLABfs Device Interoperability Level-3 (DIL-3) testing
  • Supports 8-bit or 16-bit device IDs
  • Supports incoming and outgoing multi-cast events
  • 1x/4x serial with integrated transceivers in selected device families and support for external transceivers in older device families
  • All four standard serial data rates supported: 1.25, 2.5, 3.125, and 5.0 gigabaud (Gbaud)
  • Receive/transmit packet buffering, flow control, error detection, packet assembly, and packet delineation
  • Automatic freeing of resources used by acknowledged packets
  • Automatic retransmission of retried packets
  • Scheduling of transmission, based on priority
  • Reset controller — fatal error does not require manual resetting
  • Optional automatic resetting of link partner after detection of fatal errors
  • Support for synchronizing with link partnerfs expected ackID after reset
  • Full control over integrated transceiver parameters
  • Configurable number of recovery attempts after link response time-out before declaring fatal error
  • Supports multiple Logical layer modules
  • A round-robin outgoing scheduler chooses packets to transmit from various Logical layer modules
  • Generation and management of transaction IDs
  • Automatic response generation and processing
  • Request to response time-out checking
  • Capability registers (CARs) and command and status registers (CSRs)
  • Direct register access, either remotely or locally
  • Maintenance master and slave Logical layer modules
  • Input/Output Avalon Memory-Mapped (Avalon-MM) master and slave
  • Logical layer modules with burst support
  • Message Passing
  • Avalon streaming (Avalon-ST) interface for custom implementation of message passing
  • Doorbell module supporting 16 outstanding DOORBELL packets with time-out mechanism
  • Support for preservation of transaction order between outgoing DOORBELL messages and I/O write requests
  • New registers and interrupt indicate NWRITE_R transaction completion
  • Support for preservation of transaction order between outgoing I/O read requests and I/O write requests from Avalon-MM interfaces
  • SOPC Builder support
  • IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators
  • Support for OpenCore Plus evaluation

More info: Altera