The Xilinx Virtex-6 FPGA family have fully qualified on UMC’s 40nm logic process. The qualification is the result of the close work between engineering teams from both companies to further enhance yield, reliability and cycle time. The full qualification of the Virtex-6 family signifies the transition to 40nm volume production following UMC’s first shipments of the devices in March 2009.
Built using third-generation Xilinx ASMBL architecture, the Virtex-6 FPGA family delivers 15% higher performance and 15% lower power consumption compared to competitive 40nm FPGA offerings. The devices operate on a 1.0v core voltage with an available 0.9v low-power option and are supported by a new generation of development tools delivered by ISE Design Suite 11 and a vast library of IP already available for the market leading 65nm Virtex-5 FPGA family to ensure productive development and design migration.
UMC’s independently developed 45/40nm logic process utilizes sophisticated immersion lithography for its 12 critical layers and incorporates the latest technology advancements such as ultra-shallow junction, embedded silicon-germanium and mobility enhancement techniques, and ultra low-k dielectrics. Currently, several customers have 45/40nm products being manufactured at UMC, with thousands of wafers having already been shipped.