The Cadence C-to-Silicon Compiler now features FPGA-synthesis support for Altera and Xilinx FPGAs. The electronic system-level (ESL) tool was originally focused on ASICs, but now delivers the same productivity benefits to designers of system-on-chip IP blocks targeting Altera and Xilinx FPGAs. C-to-Silicon Compiler improves designer productivity up to ten times in creating and re-using system-on-chip IP. The Cadence C-to-Silicon Compiler is designed to work with the Altera’s Quartus II software and Xilinx Synthesis Technology FPGA-synthesis tools. It is available in limited production and.
The C-to-Silicon Compiler handles mixed control/datapath designs, as well as incremental synthesis. In response to developers’ requests, Cadence applied their ELS technology to designs targeting the Altera and Xilinx FPGA families. As a result, designers now get the same advantages with high-level synthesis whether they are targeting their designs to FPGAs or to ASICs.
More info: Cadence