ISE(R) Design Suite 10.1, from Xilinx, Inc. (Nasdaq: XLNX), provides FPGA logic, embedded and DSP designers with immediate access to Xilinx’s line of design tools with full interoperability. The ISE Design Suite 10.1 delivers significantly faster implementations with an average of 2X faster run times, allowing designers to complete more turns per day. The latest release features SmartXplorer technology, which was developed specifically to address the top challenges of the design community — timing closure and productivity. SmartXplorer technology leverages distributed processing across multiple Linux machines to enable even more implementation runs per day, and up to 38% faster performance by leveraging distributed processing and multiple implementation strategies. SmartXplorer technology also provides tools that allow users to monitor each run with individual timing reports.
The ISE Design Suite 10.1 consists of ISE Foundation, Embedded Development Kit (EDK) with Platform Studio (XPS), System Generator for DSP, AccelDSP(TM) synthesis tool, ChipScope(TM) Pro analyzer and ChipScope Pro Serial I/O toolkit, PlanAhead design and analysis tool and ISE simulator. Users can install domain specific DSP, embedded and logic design products from either a DVD or electronic download. Using an electronic fulfillment process as the primary product delivery method provides users with access to not only the products they are entitled to, but evaluation versions of other Xilinx design tools. All products in the ISE Design Suite 10.1 are immediately available with prices ranging from US $495 to $2495. Full-featured 60-day evaluation versions can be downloaded from the Xilinx web site at no charge.
With the availability of the PlanAhead Lite tool in ISE(R) Foundation(TM) software, users have access to a subset of the powerful floorplanning and analysis capabilities of the award winning PlanAhead design and analysis tool. Included at no additional cost, PlanAhead Lite features the revolutionary PinAhead technology, an intuitive solution designed to simplify the complexities of managing the interface between the target FPGA and PCB. PinAhead technology facilitates early and intelligent pinout definition to eliminate many of the pinout related changes that typically happen downstream by performing design rule checks during interactive pin placement. Once the pin assignments have been completed, PinAhead provides the ability to export I/O port information through either comma separated value (CSV) files or via VHDL or Verilog headers.
With ISE Design Suite 10.1, Xilinx has also simplified the process of determining optimal implementation settings. Designers now have the ability to specify and set their own unique design goals, whether they are working to maximize performance, optimize device utilization, reduce dynamic power, or minimize implementation time. Designers using this area reduction strategy can realize an average of 10 percent better logic utilization.
The ISE Design Suite 10.1 also benefits from the efforts of the company’s joint collaboration with Mentor Graphics, one of the industry’s leading EDA providers. Through the use of IEEE IP encrypted models, ISE Design Suite 10.1 offers up to 2X faster run times. The new performance optimized BRAM, DSP, and FIFO simulation models further reduce RTL simulation run times by an additional 2X.
Industry studies show meeting power budgets is a growing challenge for FPGA designers, especially as process geometries continue to shrink. The ISE Design Suite 10.1 provides capabilities for users to analyze power requirements early in the design and optimize dynamic power throughout the design process.
The second generation XPower power analysis tool enhances power estimation by providing an improved user interface to make it easy to analyze power by blocks, hierarchy, power rails and resources used. Information is presented in both text and HTML report formats. This is a significant advance from the static estimation web pages offered by other logic providers and a leap forward in providing accurate power dissipation information.
ISE Design Suite 10.1 provides power optimization that’s both convenient and extensive. Using the integrated ‘power optimization design goal’ feature, users have a simple, one-step process to specify power optimization. With improvements in the map and place & route algorithms, users can reduce dynamic power in their designs by an average of 10 percent for 65nm Virtex(R)-5 devices and an average of 12 percent with Spartan(TM)-3 generation FPGAs.
To help users achieve optimal embedded and DSP design results more quickly, ISE Design Suite 10.1 also introduces many ease-of-use enhancements to both the Xilinx embedded and DSP tools, including unified interoperability which allows users to easily add System Generator modules within the ISE Project Navigator. Inter-tool integration enhancements between EDK and System Generator for DSP technologies enable more sophisticated FPGA SoC design incorporating both embedded and signal processing.
More information: Xilinx ISE Design Suite 10.1