SpringSoft ProtoLink Probe Visualizer

SpringSoft announced their ProtoLink Probe Visualizer. The tool increases design visibility and simplifies debugging of FPGA-based prototype boards. ProtoLink Probe Visualizer achieves a high level of design visibility and makes prototype boards easier to debug starting at the early RTL design stage all the way through final implementation. The tool shortens the verification cycle of off-the-shelf or custom-designed prototypes. The ProtoLink Probe Visualizer is available now for a list price of $40,000 (USD) for a one-year subscription license.

SpringSoft ProtoLink Probe Visualizer for debugging of FPGA-based prototype boards

ProtoLink Probe Visualizer Features

  • Synchronous and asynchronous sampling with small footprint soft IP on each FPGA
  • Probe data captured and uploaded into SpringSoft FSDB for debugging
  • Single design compilation to use Probe Visualizer and Verdi debug software
  • Probe Memory stores up to 44 million cycles without using FPGA resources
  • Probe ECO with integrated revision management system saves hours of setup time
  • Flexible hardware kit links prototype board with engineering workstation to run conventional in-circuit emulation
  • ProtoLink Interface Card bridges the workstation running the Probe Visualizer software to the prototype board via standard J-connectors or Mictor connectors
  • High-speed Fibre channel for connecting the interface card to the workstation
  • 2GB Probe Memory on the interface card to store probe data
  • Supports custom prototypes and pre-fabricated HAPS System, TAI Logic Module, and ChipIt boards
  • Reduces prototype debug time by half
  • Improves verification efficiency for early validation of SoC designs
  • Maximizes ROI with faster and earlier deployment
  • Real-time visibility into thousands of signals for millions of cycles
  • Debugs designs on prototype boards at the register transfer level (RTL)
  • Adds/changes probes in just minutes with fast ECO flow
  • Seamlessly debugs pre-partitioned designs across multiple FPGAs
  • Expands number of probe signals from 10s to 1000s with user-friendly time-division multiplexing (TDM) technology
  • Supports multiple probe groups and probe buses for viewing up to 8K signals per FPGA per probe bus at one time
  • Siloti Visibility Automation System can be used to determine minimum set of probe signals needed for optimal design visibility
  • Eases RTL debug with advanced visualization, tracing and analysis capabilities
  • Drag-and-drop probe signals between Verdi and Probe Visualizer environments
  • View waveforms and set event/triggers across multiple FPGAs to analyze design behavior and identify the root cause of bugs
  • Add/modify probes with partial routing to eliminate long recompile and debug loops
  • Maintains RTL-to-gate correlation throughout prototype debug flow

More info: SpringSoft