Wintegra UFE3 Universal Front End IP Core

Wintegra announced the availability of its third generation Universal Front End (UFE3) IP core for high channel density wireless backhaul designs. The UFE3 IP core enhances Wintegra’s cellular infrastructure solution set and offers carriers a cost effective way to migrate their current voice centric cellular solutions to high-capacity data-plus-voice capable designs. The UFE3 soft core is verified on the Altera Stratix II FPGA. A reference board is available from Wintegra featuring Altera’s Stratix II FPGA and PMC-Sierra’s TEMUX 336.

The UFE3 IP core provides great flexibility and customization, allowing customers to tailor TDM interfaces and channel densities from 24xT1/E1, 1xOC-3/STM-1, 2xOC-3/STM-1 and up to 4xOC-3/STM-1 or 1xOC-12/STM-4. Like UFE2, UFE3 continues to provide a glueless interface to PMC-Sierra’s highly successful TEMUX® family of framer and mappers, including its latest TEMUX 336 and TEMUX 168 devices, which integrate 4xOC-3/STM-1 or OC-12/STM-4 and 2xOC-3/STM-1 framer and mappers respectively.

As cellular networks expand to accommodate more and more wireless data, wireless backhaul technologies are evolving to provide higher bandwidth bidirectional communication links between cell sites and central offices. Carrier Ethernet is becoming the cost effective conduit of this combined voice and data traffic. Carriers using systems based on the UFE3 IP core plus Wintegra’s WinPath2 processors at the central office now have a highly efficient solution for a bi-directional conversion of their 8064 legacy DS0 channels to Gigabit ethernet and then utilize Carrier Ethernet as the link to remote cell sites. The UFE3 enables a fully channelized application running any protocol including PWE3 (Pseudo Wire End to End Emulation), MC/ML-PPP (Multi-Class Multi-Link PPP), IMA (Inverse Multiplexing over ATM), MFR (Multilink Frame Relay) etc. Like its predecessor, the second generation UFE2, the UFE3 also incorporates the state-of-the-art clock recovery support for SAToP (Structure-Agnostic TDM over Packet) and CESoPSN (Structure-Aware TDM Circuit Emulation Service over Packet Switched Network) for applications where accurate timing and synchronization are critical such as cellular infrastructure systems.

More info: Wintegra