Synopsys Synplify FPGA Synthesis Tools v2012.03 Reduce Runtime by 30%

Synopsys launched version 2012.03 of their Synplify Pro and Synplify Premier FPGA synthesis tools. The new Synplify 2012.03 products include a new continue-on-error feature, hierarchical design techniques, and improved algorithms that deliver faster runtimes. The latest Synplify Pro and Synplify Premier synthesis software is available now. Customers with a current maintenance agreement can download the 2012.03 release from Synopsys using their SolvNet account. The Synplify FPGA synthesis products are supported on Windows and Linux, 32 and 64-bit platforms.

The Synplify 2012.03 software release features improved synthesis algorithms that accelerate runtime by up to 30%. Synplify Premier software is also enhanced with a new continue-on-error feature. This helps FPGA designers to reduce turnaround time by enabling them to generate a report and fix all errors resulting from missing or incorrect design definitions at the end of the hardware description language (HDL) compilation step rather than incrementally fixing an error and rerunning the compile step. This capability is especially important with SoC prototypers who may not be intimately familiar with the HDL code they have to implement in an FPGA.

The latest Synopsys Synplify Premier software release further automates the process of building high reliability and fault tolerance into an FPGA design using a combination of advanced features including selective triple modular redundancy (TMR), fault-tolerant error correcting code (ECC) memories and Hamming-3 encoding for detection and correction of soft errors.

The new Synplify 2012.03 synthesis tool offers FPGA designers significantly shorter design cycles. The continue-on-error feature addresses FPGA-based prototypers’ need for fast turnaround time by eliminating the need to address errors one at a time as they are found during HDL compilation. It is especially useful for FPGA-based prototypers who may not be as familiar with the source HDL code. Instead of stopping with each error, the tool continues compilation after an error is found, generating a report of all the errors encountered so that they can be addressed at once, without re-compiling between each fix.

Synopsys’ Synplify software includes a datapath latch conversion feature to automatically convert an ASIC design to an FPGA implementation. This simplifies the process for ASIC prototypers, and makes it possible for the engineer to use a single set of source files to implement the FPGA-based prototype. In addition, users of Synopsys’ Certify multi-FPGA prototyping environment also benefit from the streamlined error-handling and conversion features in the new Synplify software, which helps speed the validation process and reduce development time.

The 2012.03 release of Synplify Premier offers enhanced support for high reliability by giving designers the ability to address radiation effects such as single event upsets (SEUs) through multiple error mitigation techniques including localized and selective TMR implementation. In addition, the Synplify Premier software can infer error correcting memory and automatically make the proper connections to take advantage of ECC memories offered by FPGA vendors. In addition, the new release also supports fault-tolerant finite-state machine (FSM) implementation using Hamming-3 encoding to automatically detect and correct single bit errors that might occur in the registers of an FSM.

More info: Synopsys, Inc.