TimingDesigner version 9.1, from EMA Design Automation, offers support for SDC, which provides the ability to interface with FPGA and ASIC design flows. TimingDesigner is a tool for interface timing design. It provides an easy to use and intuitive method for defining and analyzing interface timing requirements. TimingDesigner 9.1 will be available at the end of October starting at $2,995 and is free to existing customers with a valid maintenance contract.
Version 9.1 of TimingDesigner is the only tool that can generate SDC timing constraints from a timing diagram. This enables users to visually define design requirements and then automatically generate SDC to drive place and route. Generating SDC directly from a timing diagram removes any confusion as to the intent behind the constraints and allows users to visually debug and refine their SDC with ease. It also greatly reduces the learning curve for users new to the SDC format. TimingDesigner 9.1 also includes a number of general productivity enhancements and updates as part of the ongoing efforts to provide the highest quality timing analysis software on the market.
The initial release of TimingDesigner with SDC support focuses on the Altera FPGA design flow. Altera worked closely with the EMA development team to enable a tight, seamless interface between Quartus II software and TimingDesigner. As a result, customers can leverage the graphical timing analysis features of TimingDesigner to rapidly develop their SDC timing constraints for Altera devices, with the overall system requirements in mind.
More information: EMA Design Automation