Xilinx introduced ISE Design Suite 12.3. ISE Design Suite 12.3 supports Intellectual Property (IP) cores that meet the AMBA 4 AXI4 specification for interconnecting functional blocks in System-on-Chip (SoC) design. The latest version of ISE Design Suite features productivity enhancements to the PlanAhead Design and Analysis cockpit, and Intelligent Clock Gating support for reducing dynamic power consumption in Spartan-6 FPGA designs. ISE Design Suite 12.3 is available now for all ISE Editions. List prices starting at US$2,995 for the Logic Edition. Engineers can download full-featured 30-day evaluation versions for free.
Xilinx ISE Design Suite 12.3 Highlights
AMBA 4 AXI4 Protocol Adoption
Xilinx’s deployment of the AMBA 4 AXI4 specification means engineers will have a consistent way to interconnect IP blocks while enabling better use of design resources through the use and reuse of IP, as well as easier integration across IP providers, all in support of Plug-and-Play FPGA design. ISE Design Suite 12.3 includes enhancements to the CORE Generator tool that accelerates design time by providing access to highly parameterized IP as well as the Xilinx Platform Studio and System Generator tools that enable designers to quickly configure their system architecture, buses and peripherals. The AMBA protocol also provides designers access to established ASIC verification methodologies and existing AMBA protocol-based IP, allowing designers to easily make the transition to FPGAs as their SoC platform of choice.
Expanded PlanAhead RTL Design, Development and Analysis Cockpit
The ISE Design Suite software’s PlanAhead design tool offers a seamless “push-button” flow in addition to an advanced visualization and analysis flow. The PlanAhead tool’s cockpit also includes Project Management, Synthesis, CORE Generator integration, Floorplanning, Place-and-Route, ChipScope Pro tool integration and Bitstream generation. The entire Xilinx IP catalog, including AXI4 protocol IP cores, is directly accessible and searchable from the same design cockpit.
Intelligent Clock Gating Support for Spartan-6 FPGAs
With ISE Design Suite v12.3, Intelligent Clock Gating supports both the low-cost Spartan-6 FPGA and high-performance Virtex-6 FPGA families. Intelligent clock-gating technology features fully automated analysis and fine-grain (logic slice) optimization capabilities specifically developed to reduce the number of transitions. The technology can reduce dynamic power consumption by as much as 30% by using a series of unique algorithms to detect sequential elements (‘transitions’) within each FPGA logic slice that do not change downstream logic and interconnect when toggled. The software generates clock-enable logic that automatically shuts down the unnecessary activity at the logic slice level to accumulate power savings without having to shut off an entire clock network.