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ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

EVE is the sponsor of the 18th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2010) via their unEVErsity Connections Program. The ACM/SIGDA International Symposium on Field-Programmable Gate Arrays will take place February 21-23, 2010 in Monterey, California. The FPGA 2010 conference will feature presentations of advances in all areas related to FPGA technology.

FPGA 2010 Presentations

• Open Source Hardware: A Bad Idea?
• The Open Core Protocol (OCPIP)
• The USRP Family of Open Source Software Defined Radios
• Open Hardware Repository (OHR)
• OpenCPI, the Component Portability Infrastructure
• Experience with the NetFPGA Program
• VPR Introspective

FPGA 2010 Sessions

• Memory Efficient String Matching: A Modular Approach on FPGAs
• A Multi-FPGA Based Platform for Emulating a 100M-transistor-scale Processor with High-speed Peripherals
• Towards 5ps Resolution TDC on a Dynamically Reconfigurable FPGA
• An Architecture for Graphics Processing in an FPGA
• FPGA Implementation of Highly Parallelized Decoder Logic for Network Coding
• Application of a Reconfigurable Computing Cluster to Next Generation Genome Sequencing
• Parallel data sort using networked FPGAs
• A WiMAX/LTE Compliant FPGA Implementation of a High-Throughput Low-Complexity 4×4 64-QAM Soft MIMO Receiver
• FPGA based Chip Emulation System for Test Development of Analog and Mixed Signal Circuits
• LambdaRank Acceleration for Relevance Ranking in Web Search Engines
• Implementing Dynamic Information Flow Tracking on Microprocessors with Integrated FPGA Fabric
• A Reconfigurable Computing Paradigm for Long Lifecycle Electronic Products
• Automatic Tool Flow for Shift-Register-LUT Reconfiguration, Making Run-time Reconfiguration Fast and Easy
• Odin II – An Open-source Verilog HDL Synthesis Tool for FPGA CAD Flows
• Reconfigurable Custom Floating-Point Instructions
• A Semi-Automatic Toolchain for Reconfigurable Multiprocessor Systems-on-Chip: Architecture Development and Application Partitioning
• A Dependency Graph based Methodology for Parallelizing HLL Applications on FPGA
• LUT-Based FPGA Technology Mapping for Reliability
• Aggressive Overclocking Support using a Novel Timing Error Recovery Technique on FPGAs
• Design space exploration of throughput-optimized arrays from recurrence abstractions
• Multiplier Architectures for FPGA Double Precision Functions
• A Heuristic Algorithm for LUT-based FPGA Technology Mapping using the Lower Bound for DAG Covering Problem
• High-performance FPGA Based on Novel DSS-MOSFET and Non-volatile Configuration Memory
• Design and Evaluation of a Parameterizable NoC Router for FPGAs
• Energy Reduction with Run-Time Partial Reconfiguration
• Minimizing Partial Reconfiguration Overhead with Fully Streaming DMA Engines and Intelligent ICAP Controller
• Heterogeneous-ASIF: An Application Specific Inflexible FPGA using Heterogeneous logic blocks
• Scalable Architecture for Programmable Quantum Gate Array
• User-programmable Input Interconnect Blocks: Migrating Shifting and Multiplexing Functionality from LUTs into Local Interconnect
• Fine-Grained vs. Coarse-Grained Shift-and-Add Arithmetic in FPGAs
• DRAM-Based FPGA Enabled by Three-Dimensional (3D) Memory Stacking
• Modeling and Simulation of Nano Quantum FPGAs
• Nano-Magnetic Non-Volatile CMOS Circuits for Nano-Scale FPGAs
• FPGA-Based Prototyping of a 2D MESH / TORUS On-Chip Interconnect

More info: ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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