EVE's ZeBu Validates Diamond 38xVDO Video Engines

Posted by Ken Cheung in FPGA-based Product on Tuesday, September 18, 2007
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Tensilica, Inc., used EVE's ZeBu verification tool to validate their Diamond 38xVDO Video Engines. Tensilica's Diamond Standard Video Engines are fully programmable to support VGA and standard definition (SD, also known as D1) video codecs. The video cores are targeted at mobile handsets and personal media players (PMPs).

Architected with FPGAs, ZeBu (for Zero Bugs) is configured for designs from 12.5- to 100-million application specific integrated circuit (ASIC) gates in a compact, rack-mountable unit. It emulates designs with a speed of 20 megahertz (MHz) at the transaction level and in in-circuit emulation (ICE) or synthesizable testbench (STB) mode. It can be configured to accommodate up to 200-million ASIC gates through two interconnected units. ZeBu is used during the system-integration phase of the design cycle where multiple logic blocks, multiple chips and embedded software must be verified simultaneously. Hardware design and software development teams can share the same system and design representation, and collaborate when debugging complex hardware/software interactions.

ZeBu gives Tensilica engineers an easy-to-use and affordable solution that combines the best aspects of traditional emulation and rapid prototyping systems. It is used in Tensilica's system-level regression testing, hardware/software integration, application and codec development, conformance testing and profiling. ZeBu also proved useful in validating multi-processor synchronous debugging. In addition to allowing software engineers validate codecs, ZeBu also helped Tensilica's engineers find subtle bugs during product development related to clock tree issues missed during register transfer level (RTL) simulation.

More info:
Tensilica Validates Diamond 38xVDO Video Core with EVE's ZeBu
EVE
Tensilica

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