EnSilica eSi-RISC Development Suite v2.1

EnSilica introduced version 2.1 of eSi-RISC Development Suite. It is a platform for evaluating EnSilica’s family of eSi-RISC highly configurable and low-power soft processor cores. eSi-RISC Development Suite v2.1 is a development environment for the creation, implementation and test of eSi-RISC processor embedded application designs. The eSi-RISC family of processors for embedded systems has been extensively silicon proven in a number of ASIC and FPGA technologies.

EnSilica eSi-RISC Development Suite v2.1

The eSi-RISC Development Suite v2.1 features a new hardware evaluation platform based on Altera’s Cyclone III FPGA with rapid software development and debugging facilitated through the Eclipse IDE (Integrated Development Environment) and industry-standard GNU GCC 4.4.0 toolchain, which now offers native support for the eSi-RISC architectural features.

The eSi-RISC suite includes FPGA configurations for the complete eSi-RISC processor family, numerous application examples demonstrating how the system-on-chip peripherals can be used, and a full port of the open source FreeRTOS with lwIP TCP/IP network stack. Comprehensive documentation and a range of interactive tutorials are also included.

Non-intrusive debugging for FPGAs is provided through the JTAG hardware debugger, which provides the ability to examine data, insert break and watchpoints and control program execution, giving developers full read/write access to all variables, registers, memory and attached peripherals, while supporting single-step and step-over execution of the C code and views of the disassembly. Debugging is seamless with communication over a USB interface to a host PC with GDB, the GNU project debugger, running inside Eclipse.

The eSi-RISC Development Suite v2.1 enables developers to debug code using hardware/software co-simulation by enabling remote control of Mentor Graphics’ ModelSim from the Eclipse GDB project debugger through a network socket connection. ModelSim conveniently displays disassembled instructions as text in the wave display which is especially helpful for SoC level hardware and software debugging.

Network application debugging is also simplified with the integration of WinPcap into the new eSi-RISC Development Suite’s Instruction Set Simulator to emulate the eSi-EMAC Ethernet MAC peripheral connection. This makes it possible to run a Web Server on eSi-RISC with a live Ethernet connection serving web pages to a browser running on a remote computer.

eSi-RISC is a family of highly configurable and low-power soft processor cores for embedded systems that scales across a wide range of applications and uniquely supports both 16 and 32-bit configurations. The eSi-RISC family includes the eSi-1600 16-bit processor, eSi-3200 32-bit processor, eSI-3250 32 bit processor and eSi-3250sfp incorporating a single precision floating point processor. The processor cores feature selectable Harvard/von Neumann memory and configurable cache options. The highly pipelined nature of the design gives engineers a technology-independent solution that is ideal for both FPGA applications and ASIC technologies.

More info: EnSilica