Best Tools for Verification and Debug of FPGAs

At ESC Boston, GateRocket will conduct a class, Best Tools for Verification and Debug of FPGAs. The course will be presented by Dave Orecchio, President and CEO of GateRocket, a supplier of FPGA design and debug solutions for Xilinx and Altera programmable devices. The event will take place at 3:15 pm, Wednesday, September 22, 2010 in Room 103, Hynes Convention Center, Boston.

With improvements to the FPGA design flow, such as those that device native methodologies deliver, FPGAs will continue to grow as an important design consideration in production systems, even as platforms for complex embedded systems that contain multiple functional blocks and subsystems.

The process for identifying and fixing FPGAs by looping from the lab, where a bug is identified, back through simulation, synthesis, and place and route adds between 92 and 148 days to the FPGA design process. GateRocket has shown that its solutions can reduce this process by 55% or more by allowing the same bugs to be found and fixed during the simulation phase. By allowing the simulator to perform like the development board, many engineers would be inclined to do more of the debug there.

More information: GateRocket