EnSilica announced the eSi-1600, eSi-3200, and eSi-3250 highly configurable and low-power soft processor cores. The new processor cores are available immediately for deployment as part of EnSilica’s full specification-to-silicon design service through a number of leading foundries and an FPGA integration service utilizing devices from all the leading vendors.
The eSi-1600, eSi-3200, and eSi-3250 processor cores are based on EnSilica’s eSi-RISC scalable processor architecture, which supports both 16 and 32-bit configurations and has already been silicon proven over a number of ASIC and FPGA designs. The processor cores also benefit from selectable Harvard/von Neumann memory and configurable cache options. The highly pipelined nature of their design gives customers a technology-independent solution that is ideal for FPGA applications which can easily be migrated between FPGA types or even to ASIC technologies.
The eSi-1600 is low-power 16-bit processor that uses only 8.5k gates and delivers up to 0.7DMIPS/MHz. At only 15µW/MHz in a 0.13µ technology, it is ideal for low-cost, low-power applications such as energy monitoring, intelligent sensors, medical, and wireless networking.
The eSi-3200 is a 32-bit core designed for use with on-chip memory. This configuration is only 15k gates. The 5-stage pipeline can achieve 700MHz in a 90nm process. It delivers up to 0.9DMIPS/MHz. This core is ideal for low-power applications requiring more code space than the eSi-1600 can provide, such as wireless communications and media processing.
The eSi-3250 is optimized for use with off-chip memory and has configurable instruction and data caches (4-64kB, direct mapped or 2 or 4-way associative). In this configuration, the core is still only 20k gates. It can deliver up to 1.2DMIPS/MHz. There is an optional IEEE 754 floating point unit and MMU. The eSi-3250 is suited to a wide range of applications including running complex operating systems.
The eSi-1600, eSi-3200, and eSi-3250 processor cores feature an instruction set that has a number of optional instructions and addressing modes, as well as support for up to 96 user-defined instructions. They deliver a 40% code density saving over the soft cores typically available from FPGA vendors, saving valuable on-chip memory resources. System clocks speeds of over 200MHz can also be achieved in Altera Stratix IV and Xilinx Virtex-6 FPGAs. All processors use the industry standard AMBA APB and AXI buses. EnSilica has a growing library of APB-based peripherals it can offer, including UART, SPI, I2C, Timers and a compact 10/100 Ethernet MAC.
Industry-standard embedded development tools have been ported to the eSi-RISC architecture to create a single development toolchain that includes the GCC 4.4.0, Binutils 2.20 and GDB 7.0. These are seamlessly integrated into the Eclipse 3.5 development environment, taking full advantage of the graphical build and debug capability provided.
More info: EnSilica