CebaTech introduced their CebaRIP library of rapidly tunable silicon IP cores for system-on-chip (SoC), ASIC, and FPGA designs. The CebaRIP library features standard data encryption and compression algorithms used in storage, storage area network (SAN), network-attached storage (NAS), and network applications. CebaRIP cores can be tuned for reuse in multiple application scenarios, each with different application-specific performance, power, area and cost requirements. In addition, multiple disparate cores can be configured in a plug-and-play ensemble to boost performance and provide a system level solution. CebaTech delivers all CebaRIP cores as synthesizable Verilog RTL source code, accompanied by a simulation environment and scripts, and a comprehensive user’s guide. The CebaRIP library cores are available now.
CebaRIP Core Library
- Data Encryption Core
The CebaRIP AES data encryption core implements the Advanced Encryption Standard algorithm, and is compliant with the IEEE Standard P1619 for the cryptographic protection of data on block-oriented storage devices. It can be configured to support 128-bit, 192-bit and 256-bit cryptographic keys, and can be customized to deliver only AES encryption or only AES decryption. With a 100 MHz clock, data throughput ranges from 1 Gbps to 25 Gbps, depending upon area constraints.
- Data Compression Cores
- The CebaRIP GNU zip (GZIP) core complies with the RFC1951 and RFC1952 standards. It offers optional dynamic Huffman tables for maximum compression, and a configurable hash table width to optimize memory area. The GZIP core achieves compression ratios in excess of 2. With a 100 MHz clock, data throughput ranges from 500 Mbps to 5 Gbps, depending upon area constraints.
- The CebaRIP Lempel-Ziv Ross Williams (LZRW3) core implements the Ross Williams lossless data compression algorithm, with compression ratios in excess of 2, and data throughput of 2 Gbps, or higher.
- Data Decompression Core
The CebaRIP GUNZIP core decompresses data previously compressed by any GZIP-compliant algorithm, and is compliant with the RFC1951 and RFC1952 standards. It supports stored mode, and both static and dynamic Huffman trees, and achieves a data throughput in the range 500 Mbps to 5 Gbps with a 100 MHz clock, depending upon area constraints.
More info: CebaTech