Xilinx ISE Design Suite 12.2 and Partial Reconfiguration FPGA Flow

Xilinx introduced ISE Design Suite 12.2 and the fourth generation partial reconfiguration design flow. ISE Design Suite 12.2 features lower power consumption, reduced overall system costs, and a low-cost simulation solution for the embedded design flow. ISE Design Suite 12.2 is now available for all ISE Editions with list prices starting at $2,995 for the Logic Edition. Fourth generation Partial Reconfiguration can be purchased as an option and is bundled with two days of onsite training.

The fourth generation Partial Reconfiguration from Xilinx is easier to use and includes a more intuitive design flow and interface. Features include an improved timing constraint and timing analysis flow, automatic insertion of proxy logic to bridge static, reconfigurable partitions, full-design timing closure and simulation capabilities. ISE Design Suite 12 enables designers to target Virtex-4, Virtex-5 and Virtex-6 devices for Partial Reconfiguration applications.

Xilinx improved its Intelligent Clock-Gating technology to enable the lowering of BRAM dynamic power. Through a unique set of algorithms, the ISE Design Suite can automatically neutralize unnecessary logic activity. This is a primary factor behind power dissipation, as it enables power optimizations that were not applied at the RTL level to be implemented downstream after synthesis, thereby reducing overall dynamic power consumption by as much as 30 percent. The intelligent clock-gating optimization in ISE Design Suite 12.2 will also reduce power for dedicated RAM blocks in either simple or dual-port mode. These blocks provide several enables: an array enable, a write enable and an output register clock enable. Most of these power savings will come from using the array enable.

ISE Simulator (ISim) is now available for the embedded design flow through the Xilinx Platform Studio (XPS) and Project Navigator tools, enabling embedded designers to take advantage of the mixed language (VHDL and Verilog) simulator integrated with the ISE Design Suite. The new version of ISim has several new productivity-enhancing features, including automatic detection and listing of design memories for viewing and editing. This new Memory Editor enables designers to explore what-if scenarios using a graphical way to force a value or pattern on a signal without needing to recompile the design. ISE Design Suite 12 also makes it possible for designers to navigate to HDL source from the waveform viewer.

More information: Xilinx