Actel RTAX-DSP Space Flight FPGAs

The Actel RTAX-DSP prototype FPGAs enable hardware demonstration and timing validation of designs targeted to Actel’s RTAX-DSP space-flight FPGAs. The newly available RTAX-DSP prototype devices have the same pin assignment, mechanical footprint, and identical timing properties across the full military temperature range (-55 degrees C to 125 degrees C) as their space-qualified counterparts. RTAX-DSP space-flight FPGAs add embedded radiation-tolerant multiply-accumulate blocks to the tested and proven industry-standard RTAX-S product family. The result is a dramatic increase in device performance and utilization when implementing arithmetic functions, such as those encountered in hardware DSP algorithms, without sacrificing reliability or radiation tolerance.


Actel RTAX-DSP FPGA Features

  • Highly reliable, nonvolatile antifuse technology
  • 250,000 to 500,000 ASIC gates (2 to 4 million system gates)
  • Up to 120 DSP mathblocks with 125 MHz 18 bit x 18 bit multiply-accumulate
  • Up to 540 kbits of embedded memory with optional EDAC protection
  • Up to 840 user-programmable I/Os
  • Total Dose: 300 krad (functional) and 200 krad (parametric)
  • SEU less than 1E-10 errors per bit-day (worst-case GEO)
  • SEL immune to LETTH in excess of 117 MeV-cm2/mg
  • SEU immune to LETTH > 37 MeV-cm2/mg
  • Advanced CCGA and LGA packaging for space applications
  • Screening: E-Flow (Actel Extended Flow), B-Flow (Mil-STD-883B), and EV-Flow (Class V Flow processing as per MIL-PRF-38535)

RTAX-DSP FPGAs feature up to 120 multiply-accumulate DSP mathblocks and protection against radiation-induced single event upsets (SEU) and single event transients (SET). The RTAX-DSP FPGAs use the same 0.15 micrometer UMC wafer fabrication process and the same antifuse programmable interconnect technology that are used in the industry-standard RTAX-S FPGA family.

RTAX-DSP FPGAs offer high performance at densities of up to four million equivalent system gates and 840 user I/Os for space-based applications. The embedded DSP mathblocks feature 18 bit x 18 bit multiply-accumulate blocks enabling efficient implementation of DSP building blocks, such as finite impulse response (FIR) filters, infinite impulse response (IIR) filters, and fast Fourier transforms (FFT). Each mathblock is capable of operating at 125 MHz across the full military temperature range.

More information: Actel RTAX-DSP FPGAs