Altera’s upcoming 28nm FPGAs will feature Embedded HardCopy Blocks, 28-Gbps embedded transceivers, and user-friendly partial reconfiguration. Embedded HardCopy Blocks will improve the density and I/O performance of next-generation Altera FPGAs. High-speed transceivers will help designers implement designs such as 400G systems on a single chip without the need for costly external components. Partial reconfiguration enables designers to reconfigure part of the FPGA while other sections remain running.
- Embedded HardCopy Blocks
Customizable hard intellectual property (IP) blocks that harden standard or logic-intensive functions
- 28-Gbps Embedded Transceivers
Enable breakthrough I/O bandwidth while letting you reduce external components, I/O count, power, and cost
- Partial Reconfiguration
Helps engineers reconfigure portions of the FPGA on the fly, without any system downtime
Embedded HardCopy Blocks
The Embedded HardCopy Blocks are customizable hard intellectual property (IP) blocks that leverage Altera’s HardCopy ASIC capabilities. They are used to harden standard or logic-intensive functions such as interface protocols, application-specific functions, and proprietary custom IP. The Embedded HardCopy Blocks offer developers faster time to market for designs while also reducing cost and power.
Partial reconfiguration enables engineers to reconfigure the FPGA while other sections remain running. This is extremely important in systems where uptime is critical because it allows designers to make updates or adjust functionality without disrupting services. Lowering power and cost, partial reconfiguration also improves effective logic density by removing the necessity to place in the FPGA functions that do not operate simultaneously. Instead, these functions can be stored in external memory and loaded as needed. This reduces the size of the FPGA by allowing multiple applications on a single FPGA, saving board space and reducing power.
28-Gbps Embedded Transceivers
The 28 Gbps embedded transceivers enable breakthrough I/O bandwidth. Designers will be able to maintain design functionality while reducing external components, I/O count, power, and cost. Engineers will be able to implement next-generation designs, such as 400G systems, on a single chip, without costly external components.
More info: Altera