Virtual Conference: Maximizing the Flexibility of FPGAs

The EE Times Virtual Conference titled, Maximizing the Flexibility of FPGAs, will take place Thursday, June 24th from 11:00am to 6:00pm EDT. The virtual conference features speeches, webinars, discussion panels, and live interactive chats on the topic of programmable logic and the design flexibility it allows. The online event will take place on your computer.

EE Times FPGA Virtual Conference

  • Learn how the growing IP libraries and maturing development tools enables you to custom configure your target processor with exactly the right number of digital peripherals, hardware accelerators, and execution units to optimize system processing performance, power consumption, and bill of material costs
  • Learn how to leverage the programmable logic resources to build perfectly sized digital peripherals and optimized hardware accelerators that application software developers need to build their applications
  • Learn how to combine and trade between processors and programmable logic options to build application specific platforms that enable firmware and application software developers to build highly optimized solutions
  • Gain insights into how to best partition system components between processors and programmable logic devices according to their different and complementary processing sweet spots

FPGA Virtual Conference Sessions

  • IP and Cores: Choices, Options, and Selection
    The choices for both sources and types of IP are extensive and can be quite confusing. There are numerous options for soft processor cores, IP blocks targeting signal processing, and digital peripherals, as well as hardware acceleration of algorithms. In this session, a diverse panel of industry experts will discuss the selection of products that can both simplify the implementation of these functions, and significantly lower their system and energy costs.

  • Why Embedding A Hardcore Processor Within An FPGA Is Different This Time
    This live, ad-hoc, ‘birds of a feather session’ will the swap ideas about why embedding processors in FPGAs is different from previous similar offerings from a few years ago. What is different about the devices, the processor cores, and the development tools? Join in and participate with fellow embedded developers and moderator Robert Cravotta.

  • Development Tools: What’s Gonna Work? Teamwork!
    Increasing complexity? Shortened development time? Accelerated testing cycles? How can designers approach these serious challenges all at the same time without increasing the chances of major bugs and expensive recalls or upgrades? Panelists experienced with advanced simulation and systems integration will discuss these challenges and how programmable logic tool designers are making development tool sets that include appropriate tools for both software and hardware teams that provide opportunities for better teamwork and communication.

  • Reading The Fortunes Of The Programmable Logic Startups
    There are more promising startups in programmable logic today than at any time in recent memory. What’s driving entrepreneurs to plant their flag in this fickle territory, particularly considering that it is dominated by entrenched players? What will become of these brave firms trying to grab a foothold in a market where few have ever succeeded? Join moderator Dylan McGrath of EE Times for this discussion on the fate of the PLD startups.
  • Processing Sweet Spots: Cheaper, Leading Edge Versatility, and Lower Cost
    FPGAs are getting cheaper, a keyword that hits everyone’s sweet spot. They’re also being employed as host processing elements. The panel of technical experts will discuss how current programmable logic offerings help support the challenges and varieties of leading edge processing, and how the versatility of FPGAs contributes to maintaining an advantage for implementing leading edge algorithms that are still evolving. Panelists will also cover how designers are able to use an FPGA to lower the overall design cost and power consumption of a system by offloading heavy computations and using a less powerful processor or DPS.

More info: Maximizing the Flexibility of FPGAs – EE Times Virtual Conference