Synfora will demonstrate the enhanced versions of its PICO Extreme and PICO Extreme FPGA algorithmic synthesis design tools at the Electronic Design and Solution Fair 2009. Enhancements include QoR (Quality of Results) improvements in terms of area, timing and timing correlation, reporting and feedback enhancements, and improved code coverage for PICO RTL (Register Transfer Language). EDS Fair 2009 will take place Thursday, January 22 – Friday, January 23, 2009 in Yokohama, Japan.
Synfora will offer an informational seminar on algorithmic synthesis in complex video applications from 10:30 AM to 11:15 AM on Friday, January 23. Synfora will also deliver an overview presentations at 3:20 PM on Thursday, January 22, and at 12:45 PM on Friday, January 23. In addition, Vinod Kathail, CTO and Founder of Synfora, will make a presentation from 10:45 AM to 11:15 AM on Thursday, January 22.
PICO Extreme is an advanced optimizing compiler that exploits parallelism at all levels of hierarchy, not just the block level, to reduce design and verification time, allow designers to find the lowest cost implementation and enable very rapid reaction to changes. It is widely deployed at leading customers for next-generation SoCs and FPGAs in video, wireless, imaging and security applications.
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