New Xilinx IP Cores

Xilinx, Inc. (Nasdaq: XLNX) has expanded its catalog of no-fee intellectual property (IP) cores for designing embedded processing systems with Xilinx(R) platform FPGAs. The four new IP cores are: (1) 10/100 Ethernet MAC Lite, (2) single precision floating-point unit, (3) industry standard UART (Universal Asynchronous Receiver/Transmitter) 16450/16550 controller, (4) IIC (Inter-Integrated Circuit) interface.

The four IP cores are part of the Xilinx Embedded Development Kit (EDK), which is an integrated software solution for designing embedded processing systems. The EDK includes over 40 cores for licensing at no charge. They can be used for a wide range of applications for PowerPC and MicroBlaze processor systems. Using the EDK suite of no-fee IP cores, designers can select and build an unlimited number of configurations to meet their needs and not incur the additional costs associated with traditional IP license agreements.

The no-fee IP cores are available now, delivered with the Xilinx EDK and licensed via the online IP registration center. EDK version 9.2 is available for US$495, and includes the MicroBlaze v7 processor core with new optional memory management unit (MMU), Xilinx Platform Studio (XPS) 9.2 tool suite, software drivers, documentation, and reference design examples. XPS 9.2 supports MicroBlaze and PowerPC processing design for Virtex-5, Virtex-4, Virtex-II Pro, and Spartan(TM)-3 FGPAs. XPS 9.2 supports a broad range of computing platforms, including Windows XP (32-bit SP1 & 2), Linux Red Hat Enterprise (32-bit 5.0 & 4.0, 64-bit 5.0) as well as Solaris 9 (2.9/5.9).

Peripheral IP Cores for Xilinx Embedded Processing

IIC Interface
The IIC interface IP core provides an industry standard two wire, peer-to-peer serial bus interface for device communication. This core provides master, slave and multi-master operations, supporting 400 KHz fast mode and 100KHz standard mode.

UART 16450/16550
The UART 16450/16550 IP core works in both 16450 and 16550 modes and performs the parallel to serial conversion on characters received from a CPU and serial to parallel conversion on characters received from a microprocessor peripheral.

10/100 Ethernet MAC Lite
Optimized to provide the basic Ethernet functions with the least resources used, the 10/100 Ethernet MAC Lite supports IEEE 802.3 Media Independent Interface (MII) to industry standard Physical Layer (PHY) devices and communicates to a processor via a Processor Local Bus (PLB46) interface. This core provides interfaces for both 10 Mbps and 100 Mbps.

Floating-Point Unit (Single Precision)
The MicroBlaze soft processor has an optional configuration for implementing floating-point support via the automated Platform Studio tool suite. By comparison, the Xilinx auxiliary processor unit (APU) floating-point unit IP core is designed specifically for the PowerPC 405 hard processor core implemented in the Virtex-4 FX family of FPGAs. This core provides support for IEEE 754 floating-point arithmetic operations in single precision. Software applications can use native PowerPC processor floating-point instructions to achieve sustained performance of up to 100 MFLOPS (million floating-point operations per second.)

More info: Xilinx Embedded Processing