LEON3 SPARC Soft Processor

Posted by Ken Cheung in IP Core on Wednesday, April 16, 2008

eASIC Corporation announced the availability of Gaisler Research's LEON3 SPARC Soft Processor. eASIC and Gaisler Research migrated the LEON3 processor to eASIC's Nextreme family of zero mask-charge ASIC devices and achieved 235MHz performance, shattering the performance achievable using high performance FPGAs. Customers now have immediate access to the LEON3 processor and GRLIB IP library for implementing single chip, SPARC V8 architecture compliant, embedded systems using Nextreme devices.

LEON3 is a synthesizable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The LEON3 processor features a SPARC V8 instruction set with V8e extensions, an advanced 7-stage pipeline, hardware multiply, divide and MAC units and a high-performance, fully pipelined IEEE-754 floating-point unit (FPU). Being SPARC V8 conformant, existing compilers and kernels for SPARC V8 can be used with LEON3 to facilitate rapid development of applications.

The LEON3 processor is available immediately from Gaisler Research. The processor can be implemented in eASIC's smallest zero mask-charge ASIC – NX750LP with pricing starting at $3.95 per unit in volume. Additional IP cores, comprehensive documentation and technical support are also available from Gaisler Research.

More info: eASIC | Gaisler Research

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