At DesignCon 2012, Altera will showcase how they are solving some of the industry’s most complex design challenges through 28nm FPGA architectural innovations and advanced technologies that enable high-speed I/O performance, floating point DSP and best-in-class signal integrity. Altera will participate on industry panels, conduct a TechForum tutorial and present nine conference papers. DesignCon will take place January 30 to February 2, 2012 at the Santa Clara Convention Center in California.
Altera Panel Discussions
The Case of the Closing Eye — De-mystifying the Measurement Complexity
Modern communication systems employ complex receivers that open the closed EYE. Closed Eyes are difficult to specify so standards bodies have incorporated reference equalizers to measure the receiver stress in terms of an open EYE. Altera’s Mike Li will join this panel to explore why differences must exist between the reference EQ and efficient silicon implementation.
The Future of Measurements in High-Speed Serial Links
Altera’s Daniel Chow will participate on this panel, which will feature engineers who characterize components that run at today’s highest speeds. Panelists will share their experiences at making measurements and how they combine instruments to gain as much information as possible about a signal or system.
Altera TechForum Tutorial Session
Design & Verification for High-Speed I/Os at Multiple to >32 Gbps With Jitter, Signal Integrity
This TechForum tutorial will review the latest design and verification developments, as well as architecture, circuit, and deep submicron process (40 nm, 28 nm) technology advancements for high-speed links, with an emphasis on jitter and signal integrity for up to 10- to 32-Gbps high-speed I/Os (e.g., GbE (10G, 100G), CEI/OIF (11G, 25-28G), OTN/OTU5 (32 G), Fibre Channel (16G, 32G), and PCI Express (8G, 16G)).
Altera Paper Sessions
A 12.5-Gbps TX FFE with Floating Taps in 28-nm CMOS
A 0.1- to 12.5-Gbps transmitter (TX) with flexible feed-forward equalizer (FFE) taps, in that its number of taps, the tap positions, and the tap-weighting coefficients are programmable, is fabricated in 28-nm CMOS. Operating at 12.5 Gbps, the TX FFE consumes 10 mW and achieves a total output jitter of 23.5 ps at 10e-12 BER.
PDN Resonance Calculator for Chip, Package and Board
PDNs are important for performance but are costly. A spreadsheet method to manage RLC properties of the die package and PCB is demonstrated. The resonant frequency and peak height are calculated using closed-form EM extraction and on-die capacitance (ODC) estimates. The switch factor is calculated from the PDN current, operating frequency, and ODC, and used to drive time-domain simulation. The SPICE simulation compares the PDN impedance with the target impedance and shows the first dip and burst transient responses. Model-to-hardware correlation is achieved using clock gating techniques to produce power transients at any frequency and generate impedance plots.
Worst-Case Patterns for High-Speed Simulation and Measurement
Design and validation of high-speed serial link at multi-Gbps requires time-domain simulation and measurement. The pattern length for transistor-level simulation is limited to a few hundreds of bits due to the practical simulation time, while the pattern length for oscilloscope measurement is limited to a few hundreds to a few thousands of bits due to the record length. This is where and why “killer” patterns are needed, which are relatively short (less than a few hundreds of bits), yet induce the worst case ISI.
Investigation of Performance Challenge and Opportunity to TSV Silicon Interposer in 3D Integration Systems
This session will target at performance issue and opportunity review for 2.5D silicon interposer platform for multichip integration. A test chip has been developed for engineering evaluation of electrical and thermal performance of the silicon interposer containing both Through-Silicon-Vias (TSVs) and integrated compensation devices. The session will include the study and measurement correlation in the area of TSV loss and compensation, embedded MIM decap to system PDN, thermal considerations, die-interposer and system co-design using the test chip as an example.
The Future of Measurements in High-speed Serial Links
This panel discussion will feature engineers who characterize components that run at today’s highest speeds. They will share their experiences at making measurements and how they combine instruments because using a single instrument won’t provide enough information about a signal or system. Attendees will learn how engineers use modern RF test equipment in conjunction with oscilloscopes and BERTS to get a more complete picture of a signal’s jitter, amplitude, and bit-error rates.
FPGA Implementation of Floating-Point Matrix Inversion
This session will present the techniques necessary to build extremely high-throughput floating-point signal processing using FPGAs. The representative algorithm is the Cholesky decomposition used for matrix inversion, which is implemented using floating-point vector processing engines optimized for an FPGA architecture. These techniques can deliver one million matrix inversions per second per core, resulting in an aggregate throughput of eight million matrix inversions per FPGA. In addition, the design can be easily parameterized to support different size matrices, configurable at run time. The parallel FPGA structure allows higher sustained performance than CPU-based alternatives.
Reflection-Induced Jitter Separation Methodology and Its Applications
Reflection-induced jitter has become increasingly important as the data rate for serial communication reaches 10 Gbps and beyond because it cannot be compensated by linear equalizers, yet this jitter mechanism or component is under-investigated relative to other jitter components. From the jitter separation perspective, reflection-induced jitter remains a largely unsettled or unsolved problem. In this session, we develop a time-domain impulse/step response (IR/SR)-based reflection-induced jitter separation method for high-speed I/Os. The theoretical foundation, mathematical model, simulations, lab measurement results, and practical applications will be presented.
A New Energy-Efficient Unified High-Speed Link Architecture
In addition to performance (e.g., BER), reach distance (e.g., m) and energy efficiency (e.g., pJ/bit) have become important objectives for high-speed links. This session focuses on a new architecture utilizing devices (e.g., FPGAs) with direct optical I/Os that can overcome these challenges simultaneously as the link speed increases from 10 Gbps to 28 Gbps and beyond. Quantitative analysis and experimental measurements on the link performance, reach distance, and energy efficiency will be provided for the new link architecture, along with applications to a wide range of reach distances.
PDN Noise to Jitter Transfer in High-Speed Transceiver
This session presents a comprehensive study of noise-to-jitter transfer mechanisms in high-speed transceiver PDNs. Self-aggression and channel-to-channel PDN noise demonstrate different mechanisms in noise-to-jitter transfer. Simulations and measurements reveal that self-aggression noise manifests as correlated Deterministic Jitter (DJ), while channel-to-channel PDN noise manifests as uncorrelated and bounded Gaussian jitter. Measurement techniques in frequency-domain and time-domain are developed to quantify both types of PDN-noise-induced jitter. Modeling methodology and metric of PDN design optimization are also developed. A good correlation between predicted jitter and measurements is shown.
The Effects of a Linear Equalizer on Uncorrelated Jitter and Noise and Implications for Test
This session focuses on the study of uncorrelated jitter and noise with linear equalizers such as continuous time linear equalizer (CTLE), which is commonly implemented in a high-speed serial receiver. The variation behavior of uncorrelated jitter and noise with the DC and AC gains of a CTLE is conducted and found to be not negligible. The implementations of the new findings are used to define a new far-end signal, jitter, and noise measurement method where the signal could significantly attenuated at a higher data rate and a reference receiver with a soft or hard built-in CTLE is required.