Altera Corporation (NASDAQ:ALTR) introduced DSP Builder 8.0 for high-performance digital signal processing (DSP) designs. DSP Builder v8 features second-generation model-based synthesis technology. This technology enables DSP designers to automatically generate timing-optimized RTL code based on high-level Simulink design descriptions. With the new DSP Builder feature, designers can achieve high-performance design implementations, running at near-peak FPGA performance, in a matter of minutes. This is a significant productivity savings compared to the hours, if not days, required to hand-optimize HDL code.
Designing multi-channel signal processing datapaths in applications such as multi-carrier, multi-antenna RF processing in wireless basestations, the new DSP Builder second-generation synthesis technology delivers dramatic productivity gains. The DSP Builder tool automatically adds pipelined stages and registers, and implements time division multiplexing to generate highly optimized designs for functions such as digital upconversion (DUC), downcoversion (DDC), crest factor reduction (CFR) and digital predistortion (DPD). This greatly enhances productivity and enables users to perform system level design exploration rapidly, and to easily scale their design for varying carrier bandwidths, number of carriers, antennas, and sectors. DSP Builder version 8.0 includes design examples for multi-antenna, multi-carrier WiMAX and WCDMA DUC and DDC designs.
More info: Altera DSP Builder